UPDATE

I put 33ohm resistors on the PHI/AEC/CAS/RAS lines and my clock (without any address bus switching still) looks much better. The ripple all but disappeared.

http://forum.6502.org/images/migrated/080810-000.png

And rise time looks similar to what you get with the real deal.

http://forum ...

Thanks for the responses.

As I understand the situation, then, it's your FPGA which outputs the clock, and the noise happens when the two octal transceivers for the address bus start driving. The noise is seen at the receiver - the CPU, the 6510, but isn't at the original transmitter, the FPGA ...

Hi. I've been working on a Commodore 64 6567/6569 VIC-II replica project for a number of months now. I've written my own FPGA core in verilog and have a working prototype running on a MojoV3 FPGA development board with a custom 'hat' that I designed. If you want to know all the gory details about ...

Was this project ever finished? Curious as to whether this is in a working state.