Hello.
I can answer both of your questions posted above.
For the first question, SB and IDB (DB) are 04 due to the ALU output layer being connected to SB by dpc19_ADDSB7 and dpc20_ADDSB06. IDB is 04 also because dpc25_SBDB is connecting SB and IDB to each other. The ALU output is 04 due to the ...
Search found 3 matches
- Sun Sep 21, 2025 2:42 am
- Forum: General Discussions
- Topic: State of SB and DB buses when no receiver is connected
- Replies: 2
- Views: 2540
- Thu Jan 18, 2018 5:54 am
- Forum: Emulation and Simulation
- Topic: Visual 6502 timing query
- Replies: 12
- Views: 6296
Re: Visual 6502 timing query
An afterthought: the mention of TZPRE in Dr. Hanson's diagram really needs a horizontal negation bar over it to indicate active low.
- Sun Jan 14, 2018 9:03 am
- Forum: Emulation and Simulation
- Topic: Visual 6502 timing query
- Replies: 12
- Views: 6296
Re: Visual 6502 timing query
My thanks too, for determining TZPRE. I was also wondering what it mapped to in visual6502.
I have an additional 2 cents about its naming. In visual6502, node 792 has a name of ~TWOCYCLE.phi1 in the nodenames section. This also supports the conclusion of it being the TZPRE signal, as it has its ...
I have an additional 2 cents about its naming. In visual6502, node 792 has a name of ~TWOCYCLE.phi1 in the nodenames section. This also supports the conclusion of it being the TZPRE signal, as it has its ...