Until now, I thought that for the bus state to change, some other register that is actively connected to the bus (some data receiver) is needed
I assumed that the bus state would be high due to the Precharge MOSFETS
State of SB and DB buses when no receiver is connected
State of SB and DB buses when no receiver is connected
Hey, I thought I already understood the rules between data transfer between registers via BUS. But one thing is bothering me. I noticed that in state T1 half 2, for the data transfer instructions between registers (TXA, TYA, TXS, TAY, TAX, TSX). Visual6502 shows that the SB and DB states depend on the value of the ADDER HOLD REGISTER (the ADD/SB(0-6) and ADD/SB(7) and SB/DB signals are active).
Until now, I thought that for the bus state to change, some other register that is actively connected to the bus (some data receiver) is needed
I assumed that the bus state would be high due to the Precharge MOSFETS I used a diagram from https://lambduh.neocities.org/blocks/ to visualize the signal status. I am looking for an answer as to why the state of the SB and DB bus in my case has the value 0x4 instead of 0xff
Until now, I thought that for the bus state to change, some other register that is actively connected to the bus (some data receiver) is needed
I assumed that the bus state would be high due to the Precharge MOSFETS I used a diagram from https://lambduh.neocities.org/blocks/ to visualize the signal status. I am looking for an answer as to why the state of the SB and DB bus in my case has the value 0x4 instead of 0xff
Re: State of SB and DB buses when no receiver is connected
The situation is similar with ADC # (opcode 69) in state (T0+T2) half 2 - only the data latch is connected to the DB bus and we have active a DL/DB signal - but in this case visual6502 reports the state of the DB bus as 0xff
Does the difference result from the differences in the construction of the latch and the register?
The second difference is that in this case the PASS MOSFET is inactive (the SB/DB signal is inactive) - but so far I have treated this only as a connection of two buses that has no effect on the bus status.
I know that this does not affect the state of the registers, but I would very much like to understand where this difference comes from and what determines the state of the buses
Does the difference result from the differences in the construction of the latch and the register?
The second difference is that in this case the PASS MOSFET is inactive (the SB/DB signal is inactive) - but so far I have treated this only as a connection of two buses that has no effect on the bus status.
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markmfoerster
- Posts: 3
- Joined: 14 Jan 2018
Re: State of SB and DB buses when no receiver is connected
Hello.
I can answer both of your questions posted above.
For the first question, SB and IDB (DB) are 04 due to the ALU output layer being connected to SB by dpc19_ADDSB7 and dpc20_ADDSB06. IDB is 04 also because dpc25_SBDB is connecting SB and IDB to each other. The ALU output is 04 due to the Accumulator being fed to both of the ALU's inputs (02 each) during the preceding phase 1.
For the second question, there's a little more detail to know about the Input Data Latch (IDL). What dpc43_DL/DB connects together is IDB bus nodes and another set of bus nodes that I refer to as IDL_LINK. The "true" IDL is an output layer of the actual data latch that is connected to IDL_LINK only during Phase 1. So, no grounds are attached to the joined IDL_LINK and IDB bus nodes during phase 2, where the phase 2 node connects those bus nodes to the Power node -> FF.
Cheers,
Mark Foerster
I can answer both of your questions posted above.
For the first question, SB and IDB (DB) are 04 due to the ALU output layer being connected to SB by dpc19_ADDSB7 and dpc20_ADDSB06. IDB is 04 also because dpc25_SBDB is connecting SB and IDB to each other. The ALU output is 04 due to the Accumulator being fed to both of the ALU's inputs (02 each) during the preceding phase 1.
For the second question, there's a little more detail to know about the Input Data Latch (IDL). What dpc43_DL/DB connects together is IDB bus nodes and another set of bus nodes that I refer to as IDL_LINK. The "true" IDL is an output layer of the actual data latch that is connected to IDL_LINK only during Phase 1. So, no grounds are attached to the joined IDL_LINK and IDB bus nodes during phase 2, where the phase 2 node connects those bus nodes to the Power node -> FF.
Cheers,
Mark Foerster