To answer your earlier question, I too get 7f:800000 as my answer for 1-2, which means it was actually working, I just didn't understand how that representation was supposed to be interpreted.

If 80:800000 is -2, and following your logic, I could see that being reasonable, then it follows that 7f ...

I have not looked deeper into the woz code for some times, but I compiled a small test program with vbcc using the woz library and checked a few of your steps.
Hopefully that helps a bit?
Nope, it doesn't. It helps a lot :D

I think what is apparent is that I need to understand the FP format ...

So I'm trying to figure out what's going on here - I'm having a go at writing a high-level compiler for the 6502, and it'd be nice to have a 'float' datatype, but I'm not managing to understand '1-2' at this point :)

I wrote a little routine to convert a float to 'woz' format, and it gives me ...

... because I didn't know about it I'll grab it and take a look. Thanks again!

I wasn't expecting it to be actively destroyed, that's all. It starts off as 0xFF at the beginning of the reset sequence and state BRK3 turns it into XX. I can work around that ...

The reset sequence follows the same state transitions as BRK does, which normally results in PCH, PCL and P being ...

Well, apart from figuring out why the stack pointer is undefined :)

On an original 6502, reset does not initialise the stack pointer. So Arlet's core is correct here.

To get a sane value, you need to execute LDX #$FF then TXS.

Dave

Ok, makes sense I guess.

I wasn't expecting it to be ...

Hmm. Ok, yes I can see that if I extend the 'check' function in the testbench by another clock, A <= 0 in the clock before reset is asserted. Cool - I didn't actually know the register-updates were delayed that much.

Ok, so I can adapt the testbench to that, and hopefully we're done :) Well, apart ...

So, mea culpa.

I put (PC-1) into the reset vector, because I misunderstood one of the bus-read cycles. Putting the actual *correct* vector (of PC) into the reset vector fixed that particular issue. I can see the 'ASL A' instruction appear during the DECODE cycle:

Image no longer available: http ...

... If I put byte 0xa0 (ASL A) into memory at the location pointed to by PC ($0000), set the interrupt vector to be (PC-1) and let the clock run for a bit, I see the below ...

Forgive me if I'm being unintentionally patronizing (or clueless of the true nature of your problem), but:

0xa0 is the ...

Yep, agreed, but this is only in simulation, and I'm actually using iverilog/gtkwave, so there's no chance of the extra clock delay being introduced.

Looking at the signals, they seem reasonable - the data is appearing one clock after the address is presented. I did realise (after posting the main ...

So I'd like to use Arlet's 6502 in a design, but I'm having difficulties getting it to integrate with the blockram model I'm using. If I put byte 0xa0 (ASL A) into memory at the location pointed to by PC ($0000), set the interrupt vector to be (PC-1) and let the clock run for a bit, I see the below ...

Another vote for the Zturn , and a mention that there's now a ' lite ' version as well which has a Zynq7007S (single-core ARM) but still manages 23k logic cells for the princely price of $69 (£51) or $75 (£56) for the 7010 version. You don't get the HDMI on the 'lite boards, but the add-on "cape ...

I've been playing with Arlet Ottens core (using the stock latest code from github) on a zynq 7020. It happily meets timings (ie: post place/route) with an 11ns clock (50% duty cycle for ~91 MHz) and has the following utilisation ...