My core synthesized for 100 MHz without effort, including internal memory and peripherals, on a Spartan 6. I didn't attempt to push it harder at the time.

But it depends a lot on the device and synthesis tools, and things attached to the core. So for a fair comparison it's best if you synthesize ...

@Arlet
Would you like tell us about Fmax of your processor, please?

Hi Manili,

The 6502 address space is small enough that it doesn’t really need caches, the ram in a PLD can be used directly. But if using external ram resources retaining the caches would be a good idea. The long term goals for the project might dictate inclusion / exclusion of caches.

On a clock ...

@Dr Jefyll
Thanks for your reply. I didn't understand your problem. Do the following example help you?

One of my tests during this project was Fibonacci series generation test. So here is the Verilog code:

MEM[32814] = `LDY_IME;
MEM[32815] = 8'h07;
MEM[32816] = `LDA_IME;
MEM[32817] = 8'h00 ...

Hello guys, it's me again :mrgreen:
This is a big day for me, because I'm releasing a source code of mine in public place. I hope you guys forgive me for the delay between the opening time of the topic and the release time of the code. This is pipelined 6502 source code .
Well ... good news first ...

In my version of ISE it's called "post place & route static timing". But if you enter a timing constraint (basically just the frequency of your input clock), and then generate the design, it should give you an error if it can't meet the timing.

In the menu, there's a Timing Analyzer tool for ...

Thanks a lot Ed. I'll do it ASAP.

I'm not sure what stage in the synthesis this is, but for the most accurate result you should set a timing constraint by specifying a clock frequency yourself, and then see if the tools can meet that. If so, you can increase the number until you run into problems.

Without a constraint, you get an ...

Is it fast enough for what?! Typically you'd have an application in mind, and you'd iterate on your HDL and your synthesis tactics (maybe your placement tactics) until you get there.
Is there any article/book to read about these things and learn them by doing ? Because I learned to code Verilog ...

Hi all,
I finally decided to use PlanAhead 14.7 to synthesize the core. However the result of synthesis process is varied between 123.24 MHz - 159.5 MHz.
Below is the result of synthesis which targeted Artix-7 + some changes to defaults of PlanAhead synthesis process, like "-ram_style block", "-opt ...

Hi all,
After all, I finally found a way to synthesize the core. Does anybody know how to get the report of maximum possible frequency from Quartus II ? I don't have any board/FPGA to test the core but I want to know my processor max clock speed.
Thanks a lot.

P.S. : I'll publish the pre-release ...

The MCS6500 Family Programming Manual says on page 144: In order to know whether the vector was fetched in response to an interrupt or in response to a BRK instruction, the B flag is stored on the stack, at stack pointer plus 1, containing a one in the break bit position, indicating the interrupt ...

Hi all,
I have done the BRK and RTI instructions. And now I can say implementing other instructions, is somewhat straightforward and I think it's going to be finished until to night. My processor has still no way to handle external interrupts.
Two questions :
- After BRK, should I push B and I ...

In principle you can compare your implementation, after synthesis, for clock speed and gate count, with another implementation such as the large T65 or the small Arlet core. Your core, with the caches, will run with proportionally slower memory than a cacheless core, so you could also compare two ...

Hi all,
I have done the BRK and RTI instructions. And now I can say implementing other instructions, is somewhat straightforward and I think it's going to be finished until to night. My processor has still no way to handle external interrupts.
Two questions :
- After BRK, should I push B and I flags ...