But, what is the difference between programming this, versus programming, say a MAX 10 or Cyclone 10?
The simplest answer here is: No difference.

You'll likely be using VHDL or Verilog for your design so all the real complexities will be hidden by the (Quartus II / Prime) tool chain.

You can ...

The glitch on the left can be fixed by referencing a 1 cycle delayed copy of the pixel clock during the active display area.

The 10K20 still gives you plenty to play with.

That's a bit disappointing. How good are your soldering skills?
https://www.ebay.com.au/itm/323452201817

There saw there are a couple more cheap boards on ebay, though the associated text says they are not shipping outside the US (no good for me).
https://www.ebay.com/itm/183924586506

I was able to find reference to the linux version "90_quartus_free_linux.tar" along with an MD5 sum, but couldn't locate the file itself anywhere.

Well, this is 9.0, looks like we have a winner.

I'll see if I can find a Linux version.

Unfortunately the windows version of Quartus II 9.1 sp2 didn't offer Flex10K in the device list, though Flex10K came up multiple times in the directory structure. It might be licence locked.
Now installing 9.0 for a look.

Quartus ii 9.1 SP 2 Web Edition is probably the one you want. Later versions had the inbuilt simulator removed.

You can find the windows version on archive.org
https://archive.org/details/91sp-2-quartus-free

You can also find it at various universities for download:

Universitat Politècnica de ...

I've added some comments to the source, renamed a couple signals/variables to better names, and done some general clean up.
I also found an optimization that saved 151 logic elements while making the code a little more clear.

Your debugger is keeping track of a lot of useful information though, and there's certainly nothing wrong with that.
I'm only disassembling memory at present, though will add some more bells and whistles when it's incorporated into a design with an actual CPU to keep track of.

How very unexpected - so the idea is that it reads a chunk of memory and disassembles what it finds? (As opposed to disassembling a trace of execution.)

Yes, in fact, there isn't even a CPU in my example. You could wire it up to monitor the address bus in a complete system to track access and ...

Hi all.

It's been a while since I've posted anything here, I was sidetracked by a few *life hurdles*

One of the last FPGA projects I came up with was a 6502 disassembler written in VHDL, I thought it might be of interest to some members of the forum.

Features of note:

. Independent of host CPU ...

Happy New Year everyone.

jsii, just a suggestion for your 6502 toolbox if you haven't found it yet, and since reference to cycle counts are popping up in the thread.

Kowalski's 6502 Simulator.
It has a built in assembler and lots of debugging features, including cycle counting.

You'll find a version with recent bug fixes ...