Yep, I knew about nand2tetris and had previously looked at it but dismissed it as too simplistic. Maybe I should reconsider.

Eventually the water stored in the balloon will all leak out, but not in the short time phase 2 is low.

Does the same apply for phi1?

For all practical purposes can we ignore leakage in the visual6502 and just assume that a previously powered connection will remain powered even if temporarily ...

Thanks for your answer Ed, I would be even more grateful if you addressed points 1 & 2.

Btw, I don't have any clue what capacitance is and how it affects the holding and/or losing of value/charge.

One thing I didn't mention up to now is why I want to understand the 6502. The reason is that I'm actually a programmer and a processor would be one example of programming at the lowest level(transistor/logic gate level). I hope to get some good insights about programming, including programming in ...

Quoting from the following post:
http://forum.6502.org/viewtopic.php?p=24080#p24080
the stray capacitance of the transistors holds the value.

I was wondering what the general rules for the stray capacitance are. So how long will a previously charged polysilicon, metal or diffusion element hold ...

BigEd, I emailed Segher at the provided address but got no response so far.

I'm wondering what might be the best tool/technique to visually organize the processor? Would something like a Semantic network or a Concept map be helpful? Or are there specific tools for this task?

I'm thinking about ...

According to the dictionary a latch is:

Also called latch circuit Electronics a logic circuit that transfers the input states to the output states when signalled, the output thereafter remaining insensitive to changes in input status until signalled again

As an example see:
https://en.wikipedia ...

The following is a storage unit from Balasz diagram and the intersecting wires in the red oval do not touch each other(confirmed by visual6502). So the diagram is not totally consistent or maybe it uses the convention that a 4-way intersection means no connection.

http://forum.6502.org/images ...

Hi,

in case you are wondering why I'm asking so many questions on this board, it's because I've become obsessed with understanding what every transistor in the 6502 does. I think visual6502 is a great opportunity to really understand a processor and my interest was piqued by this blog post:

http ...

Good, didn't know that I could edit the source.

From:
https://github.com/trebonian/visual6502/blob/master/nodenames.js
irline3: 996, // internal signal: PLA input - ir0 AND ir1

But analysing the circuit I see that irline3 is actually ir0 OR ir1:

http://www.visual6502.org/JSSim/expert.html?nosim=t&find=irline3&panx=501.1&pany=69.0&zoom=12.4 ...

To the left of their right ends is indeed a diffusion connection to the positive rail - I think of that as red but I suppose it's a deep orange!


On my screen this appears as a deep orange. It is a powered diffusion, it will disappear if I uncheck the corresponding checkbox. What is the positive ...

I was wondering about the workings of the rw pad. I assume it is to signal to the motherboard when the processor wants to read data from the memory and when it wants to write. So power on rw means read, and a 0 means write? What about the situation when the processor wants to neither read nor write ...

Hello I'm perusing the javascript source code of the simulator and would like to make some suggestions. Adding a few comments at the beginning of some files would make them much easier to understand.

1. The segdefs file(these are the node definitions I suppose): https://raw.github.com/trebonian ...

If you follow the link both nodes(1329 and 1394) are at the bottom right corner:

http://visual6502.org/JSSim/expert.html?nosim=t&find=1329,1394&panx=503.0&pany=117.0&zoom=12.0

They both have an orange powered diffusion layer to their left but this is apparently separated by the polysilicon. But ...