The world would have been a different place without Chuck, and my life would have been very different.

Rest in peace.

===Jac

I just heard an outrageous claim that there are approximately 400 million cell phones in the USA. I sometimes wonder if I'm the only free individual in a thousand mile radius who doesn't own and has never owned and has no immediate plans to own a cell phone.

Mike B.

I think smartphones are ...

Welcome, Walter!

And if you want to be the first to build an expansion board for my L-Star project, be my guest! Your prize will be eternal fame and fortune(*).

===Jac

(*) Fortune not included

I don't really see why any kind of emulation is needed for single-stepping in software.

A debugger would have a table of breakpoints, and it keeps track of a "current location" (i.e. the next location to execute). While the debugger runs (i.e. the program that's being debugged is not executing) and ...

!IRQ is level-triggered, so if the interrupt handler doesn't take the source of the interrupt request away, an interrupt will occur again as soon as the Interrupt flag in the processor is set. In most cases that happens when RTI restores the flags from the stack but it can also happen when the ...

Good point, though it would somewhat defeat the point of having multiple cores (or at least, more than two), since they'd effectively be operating in a round-robin fashion rather than truly in parallel.

The clock signal for each processor would be increasingly asymmetric, so yes there's some ...

Unfortunately there will be more than one slave CPU, so this approach won't work. That is also why I need the dual-port RAM, so that the slaves do not interfere with eachother.

The idea is not restrained to 2 CPUs. As long as only one CPU at a time has a clock that's in the HIGH state, you're ...

The problem is what happens if both Slave and Master happen to assert ~ML at the same time? They'd both be halted and never recover.

If you let the two CPU's run on opposite sides of a 2-phase clock, you'll avoid this problem, and then some. The 6502 doesn't use the data bus during the first half ...

The data bus is held in High-Z mode. That's pretty much the most important thing.

The address bus stays online and doesn't change between clock pulses while RESET is active.

You have to keep RESET active for at least 2 clocks or it doesn't work correctly. I don't know exactly why this is the ...

The average IQ level of all humans on the planet lost a few points when he died. RIP.

===Jac

Talking about urban legends. A couple of years ago I have read Wikipedia's article on the 6502. I can recall that they mentioned when the person have drawn out the mask layers by hand for the 6502, not a single mistake was made.

I remember reading a quote from Chuck Peddle where he admired Bill ...

I was just reminded of this thread by an email update because I'm subscribed, so let me post a quick update that the Terasic DE0-Nano (which was unavailable for some time) is now back in stock and they made it a bit cheaper too: it was $99 before, now $79 (and if you're a student, you can get them ...

That's a great compact layout. Love it!

===Jac

Interesting!

I may have to port that to one of my FPGA boards (I have several of them because I maintain the P1V Virtual Propeller project on Github). I never had a C64

===Jac

Nice design!

Not the cheapest way to make an Apple 1 replica of course, but I guess this is closer to the original design than my L-Star which eliminates the ROM, RAM and PIA in favor of emulation by the Propeller.
===Jac