Hi

I am building a project that uses an Intersil HIN232ACPZ, which is a TTL-RS-232 level shifter like the Maxim MAX232. In fact, the two have identical pinouts and so I was wondering if they are supposed to be exchangeable. I'm asking because I don't have the Intesil part, but I've got some spare ...

What it does is use the low level P2000C BIOS driver routines whose vectors are stored on the Driver Parameter Block (DPB). You can see the form of the DPB in the block of equates at the top of the file. There are a couple of helpers:

GETOFF - get offset from DPB start address, given an offset in ...

So...

Well, this is fun. Here is some test code for the FDC.

*** WARNING Z80 MNEMONICS AHEAD. 6502 JUNKIES AVERT YOUR GAZE NOW ***



;----------------------------------------------------
; Project: floptest.zdsp
; Main File: floptest.asm
; Date: 30/05/2015 12:20:09
;
; Created with zDevStudio ...

The ROM performs a checksum at boot up, before showing the IPL prompt. The result is compared with 0FFE and 0FFF (16 bit value) and if it doesn't match it spits an error out. "BAD ROM", I think. That's what the service manual says, though I haven't read that part of the code. It's pretty obscure...

OK, I have successfully dumped the three ROMS for the P2000C:

P2000CMainROM.bin - the IPL monitor.
P2000CTermROM.bin - the terminal board ROM.
P2000CTermCharROM.bin - the terminal board character generator ROM.

See attached...

Interesting. I've never witnessed EPROM failure before. If that's the problem I'm sunk, because there are not many people I know of who have these machines, and those that do are too busy or aren't answering my messages.

@Jeff, I started thinking along those lines and dumped the EPROM using the ...

Interesting point, Peter.. On the scope it looks unclean (at high resolution), with ~600Mv of difference between peak and trough. Lowest voltage I can see is 4.83, highest is 5.47. But that is still logic high as far as I know.

Let's see what a small cap will do for it. Hmm. 100nf to 0v actually ...

Hi Jeff


I don't have a PDF editor so I am going to have to refer you to the full document:

http://electrickery.xs4all.nl/comp/p2000c/doc/P2000C-SystemRefServiceManual.pdf

I really would have preferred to paste the schematics into a new PDF!

Anyway, the main board schematics start at page 134 ...

Continuity checks out on the interface cable.

I went round the read circuit again with my scope and the only thing missing is the VCO SYNC output from the FDC. Everything else looks fine. Even tricking the data separator into reading the data gives a signal at the FDC RD line.

I'm back to square 1 ...

Can't swap it, it is soldered to the board. Maybe I should solder a header there and fit a socketed cable.

Yes... In fact it is still in there!

Yes. I put it into another machine (an Amstrad 6128 which uses the same FDC) and tried it out. No problems, it worked. Which was a huge surprise.

Incidentally, it is a PLL and it has a clever circuit that feeds a 250khz signal into the read data when the drive is not on use, to prevent VCO drift. When it reads, it asserts sync and this switches the input to the RDD line. But it uses sync to bracket the RDD signal, so if no sync, no RDD can ...

Yeah. I adjusted the centre frequency (500khz). This circuit uses the sync pulse to enable the RRD signal via a 7400. So if no sync, no read signal. I have seen this with my DSO. This is why I'm asking how sync is generated by the FDC. It must be synthesised from the input signals somehow, so I ...

I can confirm that the disk and drive both work (using special software, I can plug the drive into a PC and read the disk content). Therefore I am pretty certain the interface is faulty. On this machine it uses a VCO and PLL for timing and data separation. The FDC sync pulse is supposed to bracket ...