An arcane question for you all (posted on some other forums too).

I have a Philips P2000C with a broken floppy drive interface. It uses the NEC uPD765 FDC chip, and this has an output on pin 24 called VCO Sync. It is used to bracket the RDD pulses coming off the drive.

Now on mine, it is low all the time (it's supposed to go high before each read data pulse, then low after). However, I swapped the FDC into a known working machine that uses the same chip and proved it is working, so something else is not right with the P2000C.

My question is, how does the FDC generate Sync pulse? What inputs does it use to synthesise the signal? I know it has a programmable delay (to wait for the heads to settle down after loading) before it kicks in, but mine is contestanly low and I can't see why.

Any ideas?

Are you sure it's not the diskette ?
Some methods of synchronization use data patterns stored on the drive, For instance for a 256/512 byte data sector has a preamble that may consist of a number 0xFF bytes. Because the drive controller knows how many 0xFF bytes there should be leading a data sector, it can generate synchronization timing from that, and the placement of data bits. Can you tell if the drive is getting any read data pulses at all ? It could be something in the drive head / amplifier.
Another place where synchronization is generated is from timing the rotation of the diskette. Some diskettes have a little hole in them that triggers a sensor as the disk rotates in order to measure the rotation rate. If that sensor were shot there would be no pulses for timing the rotation rate. But I believe this is quite an old way of timing, and not likely used by the system you're looking at.

_________________
http://www.finitron.ca

I can confirm that the disk and drive both work (using special software, I can plug the drive into a PC and read the disk content). Therefore I am pretty certain the interface is faulty. On this machine it uses a VCO and PLL for timing and data separation. The FDC sync pulse is supposed to bracket the incoming data on pin 30 of the drive cable (Shugart standard, it is called RDD). I can see a pulse there. Also, there is a pulse on the index pin, so that is working (it's 200uS which is correct for the application which is 300 RPM). But the VCO/PLL circuit uses the Sync pulse to enable RDD, but there isn't one, hence my question. What I am really asking for is guidance on how the Sync is generated inside the FDC, so that I can check the FDC inputs that influence it.

Hi jonb,

typically floppies for small systems do not make use of any sync pulse (INDEX, SECTOR etc.) but just write FM or MFM coded signals on the magnetic tracks. So when reading from the floppy the only signal that carries a signal that is used is RD from the floppy to the controller. The signal contains both the data and the clock of the originally recorded data. The FDC then needs some logic to separate clock and data. The clock regenerated from the signal typically is a created by the separator or a PLL. Without an oscilloscope and schematic it is very difficult to analyse what's going on. If you have an oscilloscope you can view RD from the floppy when the corresponding DS (drive select) and MOTON (motor on) is asserted (low). A head-load mechanism was mostly not implemented with 5 1/4 inch drives and there is also no such signal on the standard 34-pin cable for that. The RD should be visible at the input to the PLL and to the FDC (Pin 23 RDD) and on the output of the PLL which is connected to Pin 22 RDW (read data window) you should see a clock that is in sync with the bits (each change in bits of the stream recorded should result in a peak of the RD from the floppy). Try to just assert DS and MOTON (the interface is open collector, so you can just short them, even when the floppy is connected to the system, just never touch WG when you have a precious floppy inserted)

If you have no oscilloscope you need at least a frequency meter to check the frequency at Pin 22 is in line with the recording speed of the Floppy. Typically when you can't read with a FDC the center frequency of the PLL is off. There should be a trimer, you can try to adjust it until you can read a sector.

cheers

Peter

Yeah. I adjusted the centre frequency (500khz). This circuit uses the sync pulse to enable the RRD signal via a 7400. So if no sync, no read signal. I have seen this with my DSO. This is why I'm asking how sync is generated by the FDC. It must be synthesised from the input signals somehow, so I figured that if I checked all of those I might find one that isn't working.

Incidentally, it is a PLL and it has a clever circuit that feeds a 250khz signal into the read data when the drive is not on use, to prevent VCO drift. When it reads, it asserts sync and this switches the input to the RDD line. But it uses sync to bracket the RDD signal, so if no sync, no RDD can get to the FDC..

Every tried to replace the uPD765? Or is it soldered into the computer?

Yes. I put it into another machine (an Amstrad 6128 which uses the same FDC) and tried it out. No problems, it worked. Which was a huge surprise.

In the spirit of "check and double-check", did you also swap the FDC from the Amstrad into your Phillips machine to see if that worked? (The theory being, if the Phillips machine uses a feature of the FDC that the Amstrad doesn't, then a slightly-blown FDC could work well enough in the one, but not in the other.)

Yes... In fact it is still in there!

Hi jonb

so swapping FDC or Floppy does not receal the problem. How about the ribbon cable? Did you check or swap that one?

cheers Peter

Can't swap it, it is soldered to the board. Maybe I should solder a header there and fit a socketed cable.

So if I understood that right, everthing, that is uPD765, Floppy and Diskette, works outside the P2000C but not in the P2000C? If that's the case I would take the ohmmeter and carefully check all cables and solder points.

Continuity checks out on the interface cable.

I went round the read circuit again with my scope and the only thing missing is the VCO SYNC output from the FDC. Everything else looks fine. Even tricking the data separator into reading the data gives a signal at the FDC RD line.

I'm back to square 1 here. Looking at the status bytes it returns when reading, which appear to say "ready state changed". I don't know how that can be, when the FDC RDY line is held high all the time by the circuit. But I am beginning to suspect that that is why there is no SYNC output - the FDC is erroring out before getting to the "assert sync" part of the read operation.

Are you able to post the pertinent P2000C schematic portions for us to ponder? And -- sorry if this was mentioned already -- is the 5 volt supply, measured right on the FDC chip, clean & healthy?

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html