The ASL is used to clear the carry flag, so that the output function is bijective (invertible). The first part of the code

CLC
LDA #1 ; any odd value
ADC s+0
STA s+0
ADC s+1
STA s+1

has a cycle length of 65536, going through each 16 bit value exactly once before repeating. However, the random ...

To make neat soldering easier, I highly recommend Loctite Crystal 511. It's such a joy to work with.

In my understanding, a fill is simply a big polygon filled with copper that's connected to a specific net. In the case of ground fills, it's usually the same shape as the board outline.
That's a ground plane. By "fills" or "pours," we're talking about filling smaller blank areas here and there on ...

For hand soldering, or home reflowing in a toaster oven, it's not a problem to put a via inside a pad. It will suck up some solder, but you can always fix that.

Off topic, but may be interesting to some. I've (finally) released a version of a pseudo random generator for Microchip AVR / Arduino.

When I announce a period for my algorithms, they remain random throughout the period. You have to do the same otherwise it's cheating for the challenge :lol: I too can create an algorithm with a period of 2^1024 but which will only be random on 100 KB :
It's not cheating. It's just a different ...

You said that your last algorithm produces 2^48 bytes before looping, that's not what Practrand says. Here is my code, here are the results with only the o+3 output

It's not looping, though. It fails random tests before looping. Imagine you have a simple 64 bit counter, it wouldn't be random ...

Shouldn't you also restore your 'array' contents ?

The main part is only 65 cycles. Did I win the fun challenge?

Not quite. My code produces 32 bits at a time, and it's only 80 cycles when you put all the variables in zero page, so that's 20 cycles/byte. On the other hand, the random quality of my output is considerably lower. For a real apples ...

I don’t see an issue with the apparent “expense” of the linked nybble swap. If performance truly is a concern, then it’s time to crank up the clock speed or use the 65C816 and rewrite the code to do byte-swaps in a word for a potentially better effect on quality.
The challenge of the project is ...

I have a huge choice of 12 cycle sequences, and it's not very likely that this (admittedly clever) sequence is optimal for the purpose of mixing bits randomly.
Specifically, I think that a simple 4x ROL instruction sequence would work equally well, as long as we treat the C flag as part of the ...

In my understanding, a fill is simply a big polygon filled with copper that's connected to a specific net. In the case of ground fills, it's usually the same shape as the board outline.

But you've twice mentioned plenty of vias, presumably to Gnd, and I infer that your goal is to carry return ...

I don't agree with the advice on copper fills. I use them all the time. On a 2-layer board, I do a GND fill on both sides, and then provide plenty of vias to connect them. Track and spacing are set to minimum, and vias are used liberally to avoid long continuous traces that chop up the fills. Buses ...

If all modern CPUs use master-slave flip flops, does that mean the PC has to be copied to the address bus register a cycle ahead of time?
In a sense, yes. At every cycle N, you have to figure out, using the current state and inputs, what you're going to load in the registers on cycle N+1. If you ...

All modern logic uses master slave flip flops. Latches are only used in a few specialty circuits. Older logic, such as the NMOS 6502, used latches throughout the design. In theory, taking a flip flop apart into 2 latches and then separate them, gives you more design flexibility. In practice, it's ...