Single meaning, that the output changes as soon as it gets written to, vs double, as in a "slave-master" flip-flop where the second latch waits for the first latch to finish latching before it updates the output.

The fact that most websites describe the fetch cycle in the fetch-decode-execute pipeline is "Program counter gets copied to address bus output register, and fetches the instruction" which implies that it uses a single latch. However, I know that CPUs are supposed to keep the bus latency to a minimum which kind of implies that they use double latches, but if that is the case, then the "fetch" cycle would simply be just preparing the next address, and the "decode" cycle would be fetching the memory for real, and the "execute" cycle would be doing both the actual instruction decoding and executing at the same time. Or maybe the memory address gets output from the second half of the fetch instruction, and the actual instruction decoding starts in the second half of the decode instruction.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

All modern logic uses master slave flip flops. Latches are only used in a few specialty circuits. Older logic, such as the NMOS 6502, used latches throughout the design. In theory, taking a flip flop apart into 2 latches and then separate them, gives you more design flexibility. In practice, it's not worth it, because the gains are small, and timing analysis gets a lot harder.

Statements such "Program counter gets copied to address bus output register" should not always be taken literally. There's an address bus output register, and that gets loaded with the output of a combinatorial logic tree, which has the program counter as one of the possible inputs. For instance, there could be a program counter register, and there could be a case where you need to increment PC and then transfer AB <= PC. While that is a natural way to describe things, the reality is that PC <= PC + 1 happens in parallel with AB <= PC + 1 so it can be done in a single cycle.

If all modern CPUs use master-slave flip flops, does that mean the PC has to be copied to the address bus register a cycle ahead of time?

In a sense, yes. At every cycle N, you have to figure out, using the current state and inputs, what you're going to load in the registers on cycle N+1. If you don't know yet what to do, because you're waiting for a decoder, then typically you simply increment the address bus register, because that's most likely to be correct. If it turns out that was not correct, for instance because you needed to take a branch instead of continuing straight, then an extra delay cycle gets inserted to catch up.