VIA shift bit counter logic is extremely minimalist in terms of transistor count:

https://raw.githubusercontent.com/ijor/VIA6522/main/ViaShiftBitCounter.pdf

Obviously a simple binary counter is not efficient because the carry chain is very expensive. I expected a traditional 4 bits LFSR design ...

Right now it's all speculation, and speculation won't bring us far.

I'm not speculating. I'm commenting what I see at the chip layout. I'm not ready to post full schematics yet, but I can post seudo code of the relevant logic if you want.

I think I figured out the issue about this supposed bug ...

Hi Ed,

Discussed in 2010... see around here:
http://forum.6502.org/viewtopic.php?p=9829#p9829


Yes, I've seen that discussion, but it doesn't add any details. It actually just references wikipedia, again, as the main source without much confirmation or elaboration.


Seems possible that ...

Quote from wikipedia:

Aside from the aforementioned shift register bug, there was a potential register corruption problem that usually only occurred in systems using the 6522 with a microprocessor having a non-6502 bus architecture, such as a Motorola 68000. If the address lines changed while chip ...

I think that I'm aware of the importance of the capacitive features. Thanks for pointing that out, not all of the readers might be aware of it.

I understand. Sorry that I might have implied you are not familiar with this kind of logic.

... and some years ago I did an experimental TTL ...

I think that the schematic is more easy to understand when drawing transparent latches instead of dynamic latches.
Also, I think it simplifies things for those who might want to try simulating the circuitry.

Well, might be a matter of personal preferences. But be aware that a dynamic cell can't ...

Felt a need to re_draw your schematics

Sure. I actually appreciate it because, as it might be obvious, I'm not very good at drawing schematics.

A small comment though. The gates you draw as transparent latches are actually dynamic delays, or dynamic latches if you want. They retain the state ...

Fortunately it's only in the one SR mode (out of seven) and won't affect most users.

Why one mode only? It should affect both modes that use an external clock, shift in (mode 011) and shift out (mode 111).

Anyway, it wasn't my intention at all to complain or to criticize the VIA :) I just ...

I don't know much about the 6522. No of the systems that I specialize uses a VIA. But I recently found out about the SHIFT external clock bug, that happens to be almost exactly the same as a chip that I do am familiar. So I was very curious and reverse engineered the VIA 6522 external clock logic ...

Anyone can explore the behaviour of the NMOS 6502 using the visual6502 model, which now allows you to run a program of your choice and tabulate the bus and signal activity per clock phase.

Thanks, Ed.

This shows, btw, that it is not exactly one cycle later, but half cycle later instead. Probably ...

Yes, the half carry flag is produced in the ALU, but I was talking about the decimal adjust logic block between the SB bus and the accumulator.

Oh, I misunderstood you, sorry.

Yes, that is performed one cycle later. I thought you meant that an extra cycle is taken specifically for decimal mode ...

Looking at the 6502 block diagram, they have a separate Decimal Adjust Adder, that adjusts the byte that's loaded into the Accumulator.

The DAA consists of two 4-bit wide adders, performing an add between the ALU result, and a constant, which is equal to:

6 when the (half)carry bit is set after ...

I think I can understand the netlist description. Let's see if I'm correct:

The actual netlist is in transdefs. This files describes transistors in the format:

transistor_number,source_node,gate_node,drain_node

transdefs doesn't include depletion load transistors. They are described in segdefs ...

But because it's at transistor level, and because there are bidirectional pass gates, you'd need the right kind of simulator...I don't know about verilog (and therefore about FPGA) - if you have good ideas about modelling bidirectional pass gates then we can try it.

Verilog would do it (doesn't ...

For chips which were built from a standard cell library it's quite a bit easier as you can identify the groups of transistor in the cell and replace those with a logical equivalent. I've build up a library of such models.

Hi Mike. You might know better than me, but I don't think there was such ...