Hi guys
I've setting up an SBC design at the moment which will involve an SAA5050 Teletext Character Generator IC as part of it's video circuitry.
That chip requires two inputs: 6MHz to the TR6 pin and 1MHz F1 pin.
PHI2 is going to be switchable between 16MHz and 8MHz from a 32MHZ Source oscillator and then run through a D flip flop for a 50-50 duty cycle.
From what I can find (and anyone familar with the SAA5050 is free to correct me if I am wrong), all of those clocks need to come from the same clock source.
As such, I am going to run the 32MHz into the GCLK of an ATF1508AS 7.5ns CPLD and then output them. It looks like it could work but I was wondering it's not best to run the clock into a 74AC245 or 74HC245 buffer (or better yet a schmitt inverter 74HC14) and then out? I am a bit concerned about the output voltage and drive of the CPLD. I think it should be ok but maybe do it for robustness?
Video by the way is going to run from a a Motorola 6845 attached to an 8 or 16KB block of dual port ram so it can run slower than PHI2.
This is in the early stages so is definitely adjustable.
Any thoughts?
And if anyone has experience dealing with the SAA5050 and any gotchas any advice would be appreciated.
CPLD driven clocks sanity check
Re: CPLD driven clocks sanity check
banedon wrote:
Hi guys
I've setting up an SBC design at the moment which will involve an SAA5050 Teletext Character Generator IC as part of it's video circuitry.
That chip requires two inputs: 6MHz to the TR6 pin and 1MHz F1 pin.
PHI2 is going to be switchable between 16MHz and 8MHz from a 32MHZ Source oscillator and then run through a D flip flop for a 50-50 duty cycle.
From what I can find (and anyone familar with the SAA5050 is free to correct me if I am wrong), all of those clocks need to come from the same clock source.
As such, I am going to run the 32MHz into the GCLK of an ATF1508AS 7.5ns CPLD and then output them. It looks like it could work but I was wondering it's not best to run the clock into a 74AC245 or 74HC245 buffer (or better yet a schmitt inverter 74HC14) and then out? I am a bit concerned about the output voltage and drive of the CPLD. I think it should be ok but maybe do it for robustness?
Video by the way is going to run from a a Motorola 6845 attached to an 8 or 16KB block of dual port ram so it can run slower than PHI2.
This is in the early stages so is definitely adjustable.
Any thoughts?
And if anyone has experience dealing with the SAA5050 and any gotchas any advice would be appreciated.
I've setting up an SBC design at the moment which will involve an SAA5050 Teletext Character Generator IC as part of it's video circuitry.
That chip requires two inputs: 6MHz to the TR6 pin and 1MHz F1 pin.
PHI2 is going to be switchable between 16MHz and 8MHz from a 32MHZ Source oscillator and then run through a D flip flop for a 50-50 duty cycle.
From what I can find (and anyone familar with the SAA5050 is free to correct me if I am wrong), all of those clocks need to come from the same clock source.
As such, I am going to run the 32MHz into the GCLK of an ATF1508AS 7.5ns CPLD and then output them. It looks like it could work but I was wondering it's not best to run the clock into a 74AC245 or 74HC245 buffer (or better yet a schmitt inverter 74HC14) and then out? I am a bit concerned about the output voltage and drive of the CPLD. I think it should be ok but maybe do it for robustness?
Video by the way is going to run from a a Motorola 6845 attached to an 8 or 16KB block of dual port ram so it can run slower than PHI2.
This is in the early stages so is definitely adjustable.
Any thoughts?
And if anyone has experience dealing with the SAA5050 and any gotchas any advice would be appreciated.
Good luck! Sounds like a nice retro style project.
-Gordon
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/
Re: CPLD driven clocks sanity check
drogon wrote:
banedon wrote:
Hi guys
I've setting up an SBC design at the moment which will involve an SAA5050 Teletext Character Generator IC as part of it's video circuitry.
That chip requires two inputs: 6MHz to the TR6 pin and 1MHz F1 pin.
PHI2 is going to be switchable between 16MHz and 8MHz from a 32MHZ Source oscillator and then run through a D flip flop for a 50-50 duty cycle.
From what I can find (and anyone familar with the SAA5050 is free to correct me if I am wrong), all of those clocks need to come from the same clock source.
As such, I am going to run the 32MHz into the GCLK of an ATF1508AS 7.5ns CPLD and then output them. It looks like it could work but I was wondering it's not best to run the clock into a 74AC245 or 74HC245 buffer (or better yet a schmitt inverter 74HC14) and then out? I am a bit concerned about the output voltage and drive of the CPLD. I think it should be ok but maybe do it for robustness?
Video by the way is going to run from a a Motorola 6845 attached to an 8 or 16KB block of dual port ram so it can run slower than PHI2.
This is in the early stages so is definitely adjustable.
Any thoughts?
And if anyone has experience dealing with the SAA5050 and any gotchas any advice would be appreciated.
I've setting up an SBC design at the moment which will involve an SAA5050 Teletext Character Generator IC as part of it's video circuitry.
That chip requires two inputs: 6MHz to the TR6 pin and 1MHz F1 pin.
PHI2 is going to be switchable between 16MHz and 8MHz from a 32MHZ Source oscillator and then run through a D flip flop for a 50-50 duty cycle.
From what I can find (and anyone familar with the SAA5050 is free to correct me if I am wrong), all of those clocks need to come from the same clock source.
As such, I am going to run the 32MHz into the GCLK of an ATF1508AS 7.5ns CPLD and then output them. It looks like it could work but I was wondering it's not best to run the clock into a 74AC245 or 74HC245 buffer (or better yet a schmitt inverter 74HC14) and then out? I am a bit concerned about the output voltage and drive of the CPLD. I think it should be ok but maybe do it for robustness?
Video by the way is going to run from a a Motorola 6845 attached to an 8 or 16KB block of dual port ram so it can run slower than PHI2.
This is in the early stages so is definitely adjustable.
Any thoughts?
And if anyone has experience dealing with the SAA5050 and any gotchas any advice would be appreciated.
Good luck! Sounds like a nice retro style project.
-Gordon
. The circuit used by the BBC is based on an interesting hack for getting a 6MHz signal out 4MHz & 8MHz clocks generated by Vidproc using some inverters, an SR lathc and other gates.