VIC 20 6502 clock conundrum

[Charlielamus]

Hi guys,

I am trying to understand the VIC 20 schematic as an intellectual exercise, and I have come across a bit I don't understand - can anybody help?

The bit in question is the clock pin. As it currently is, there is a clock feed taken off to go elsewhere, but rather than simply coming from Phi2 (shown as Phi0 in this diagram), the feed is NORd with PhiO2 (which I thought was just the clock sent straight back out again) and then inverted.

Does anybody know why this is? Is it for complicated timing reasons) And would it be necessary with a W56C02 or can I just tap the clock in feed and leave it at that?

Thank you!

[fachat]

Interesting. This basically delays the falling edge by the phi0-to-phi2 delay, and the whole clock by two gate delays.
But no idea why it does so.

[richardc64]

The NOR and inverter generate what the schematic call SØ1 and SØ2. SØ1 enables BLocK0 (the lowest 8K segment of memory) shared with 6560 Vid Controller during the video phase, and SØ2 enables any resource -- including BLK0 -- during the cpu phase. NORing Ø1 out with Ø0 in and inverting the result makes SØ2 fall around 20nS after Ø0 falls. I don't know why that was necessary, but yes, maybe it had something to do with the timing for the VIAs and/or the slow (at the time) static RAMs that were used.

All of which doesn't matter for a 65C02, as I found out. However, replacing the NMOS '02 with a 'C02 without preparation isn't a good idea. Pin1, VPB on the 'C02 is an output. On VIC's pcb it's GND! Fortunately for me I didn't keep the 65C02 in my VIC very long because I wanted to save it for the modifications I plan for VIC innards. It remains to be seen whether the short time I had VPB out shorted to Ground did any harm to the chip.

But wait, there's more. Pin2, ReaDY on the 'C02 is bidirectional. On the pcb it shares a pullup resistor with SOB (SOV). So a low RDY out, caused by WAI would cause an unexpected SET V. ALSO, pin 36, Bus Enable is No Connection on VIC's pcb -- floating. When I'm ready to install WDC65C02 permanently I'll do this:

Regards,
Richard

[John West]

Phi0 and phi2 are labelled correctly according to the CSG datasheet I have (it seems to be from 1985). Pin 37 is phi0, pin 39 is phi2. The NMOS 6502 has a clock generator which takes a single clock input (phi0) and generates the two non-overlapping clocks it needs internally (phi1 and phi2). Bus timing is referenced from phi2.

The output of this NOR gate is used in the generation of chip selects for the RAM, so it must include phi2. That's going to trail phi0 by some unknown amount. Including phi0 as well will select chips a little bit earlier, giving slow devices more of a chance to respond.

The 6502 needs read data to be valid from 100ns before phi2 falls, and chip selects for the ROMs (which are also gated by this signal) go through a 74LS138 with its own delay of up to 40ns. The pulse width of phi2 is 40ns less than that of phi0 (there are generous gaps to ensure that phi1 and phi2 don't overlap). That doesn't leave enough time for the 350ns ROMs to respond unless you use phi0 to select them a little earlier.


The W65C02 also generates phi1 and phi2 but its bus timing is referenced from the input, which they confusingly also call phi2. This is an important difference from the NMOS 6502. That input is not going to have the 40ns shortening that the NMOS chip's phi2 output did. Also, its data setup time is considerably shorter. The ROM will have plenty of time in that case, and you should be able to use the phi2 input directly.

Actually, I think you might have to. Falling edges of the output phi2 will come some time after the falling edges of the input, and that might leave the RAM enabled after write data has become invalid. tDHW is only 10ns.


TLDR: It's complicated timing reasons, and the NMOS 6502 and W65C02 are very different. You can't use knowledge of one to try to understand what the other is doing.

[Charlielamus]

Brilliant, thank you all.

Just to be specific about what I am mulling over, I am wondering how difficult it would be to make a breadboard VIC 20 compatible, still using the VIC chip but stripping out much of the I/O like the light pen and the disk drive stuff, and installing all of the possible ROM and RAM from the word go, thus removing the need for some of the bus control logic.

I'll carry on mulling!