The ATF750C : Charm and Strangeness (*)
Posted: Thu Jul 17, 2025 1:47 pm
[NOTE: all references to '750 in this document refer to the 'modern' CMOS PLD devices "ATF750C" or "ATF750LVC", not the older V750, 750B GALs ]
Whenever I've seen references to the ATF750 on the net it's nearly always called "a 22V10 on steroids". I suppose in some ways it's true, but I think it's rather 'cliché', as they say here in France
In this thread I'll document my discoveries about this unfortunate "black sheep" of the Atmel ATFxx series PLDs. Black Sheep for a major part in that very few PLD programmers actually know/care about it, probably due to some very wierd programming algorithms...
I'll talk about a fairly affordable DIY and open source solution for the programming later-on. I'd like to talk about the Charm and strangeness first.
The Charm
The device's pin configuration is identical to the 22V10. The "750C" version is a 5v beast, but there is an "LVC" version which can be used at 5v or down to 3.0v. Even when used at 3v, the inputs are 5v tolerant - which makes the device quite useful for interfacing. The ATF750LVC is available as 24-pin DIP but also in PLCC, SOIC and TSSOP formats. I'm not sure, but AFAIK there is only one speed option for the LVC, the "-15", which is rated at 15nS maximum propagation delay (pin-to-pin) *AT 3V* (the datasheet says 10nS max. at 5v). So a good candidate for address space decoding, or for latching the extended address lines from a 65816 (see example 1).
From the outside the '750 looks like a 22V10 - but under the hood there's a much bigger motor...
To start with, there's twice as many accessible registers. This is achieved by splitting each of the 22V10s original registers into two independant Flip-Flops, and providing access to each of them via buried nodes (see table, below). Each of the F/Fs provide internal feedback, and 10 have the output drivers for driving the O/P pins. Each F/F can be individually configured as D-type or T-type (toggle) - using the terms xxx.d or xxx.t.
Note that combinatory logic still has the same large fan-in (note the switch symbol between the two F/Fs) : each half has from 4 to 8 product terms, the two sides are then summed.
As with the 22V10, pins 14..23 on the '750 are configurable as Output or Input. Combinatory declarations will automatically configure a pin as Output, and will transparently enable the output enable term '.oe'. Registered declarations (i.e. using the F/F) can use the pin's Q0 F/F as a 'buried' node and define the pin as an input by forcing the '.oe' term to zero. It's even possible to use the pin as input AND output by careful synchronization of the register clocks and the '.oe' terms.
While talking about inputs and outputs, it's worth mentioning that the "polarity" of each pin (i.e. active high or active low) is defined in the PINS declaration. By default a pin is active high, to make it active low you simply place the '!' character in front of the pin name (e.g. !WR).
The next feature is that each F/F has it's own individual clock line with a selection switch to either use the 'master' clock (Pin1), or an internal signal, either a physical signal or a combinatory term. Each F/F clock can be either synchronous (by specifying '.ckmux'), or asynchronous (by specifying '.ck'). See the EX375 example, below.
And, to finish the list, each F/F has it's own Asynchronous Reset term, '.ar'.
The Strangeness
There were probably some compromises made in order to squeeze all this into the small package, the biggest and strangest of all is that the Synchronous Preset term '.sp' is GLOBAL - it affects ALL of the F/Fs. If you declare it, it will become global for all registers. WinCUPL also makes things stranger because it knows about this "feature" and will report an error if you declare more than one '.sp' term, but will all the same issue warnings for all the other used registers that don't have their sp term declared.
The rest of the strangeness is the programming algorithm, which seems to have been held "top secret" since the existence of the V750B GAL.
Very few affordable programmers are able to program the 750 series.
Programming
One affordable version, which is tailored very much to the Atmel series of GALs and SPLD devices, is the open-source afterburner project. The programmer itself is a board that plugs onto a standard Arduino controller, it holds a 24-pin ZIF socket and a programmable voltage source for the different Vpp voltages.
The Arduino does all of the actual programming stuff, and it is 'driven' by a simple command-line interface that is compatible with Win, Mac and linux. The project maintainer, Alexander Shniperson ("ole00"), has also designed some special carriers that fit onto the ZIF socket to allow programming of different package outlines. Full build and calibration details are provided, along with the gerber files to send to your favorite pcb manufacturer. The board is easy to assemble and has footprints for both through-hole and SMT components. You'll need a programming environment for the Arduino (the klunky IDE is OK for this).
A big note, though : if you want to program the ATF750 or the ATF1500 family you should choose an Arduino Mega 2560 controller : it has the memory capacity on-board to handle the large fusemaps of these devices. I have been using afterburner to program 8V16 and 22V10 devices for over a year, and have worked with Alexander to iron-out a few problems that were encountered with the ATF750. And it works !
I have attached the ATF750LVC datasheet and, more importantly, a very useful Atmel application note about using the '750s features.
Examples
The first example is a slightly modified form of one of BDD's POC experiments. In his design he was feeding the decoder with both PHI2 and PHI1 (antiphase), and at the same time was eliminating any clock assymetry - a requirement at high clock speeds. I'm currently "messing about" with a redesign of the RP6502 'picocomputer' (using a pi pico to 'drive' the 6502) to incorporate the 65816. I'm not running at breakneck speeds (yet) and as the pico is a 3v device I'm glad to have a cheap and simple PLD that works well at 3v. As it's the pico that supplies the PHI2 clock, I need to have an inverted clock to be able to latch the extended address from the data bus. The declaration in the WinCUPL PLD file is simple, and it works. I haven't yet measured the propagation delay nor experimented with other feedback paths to see what effect they have. I'll update this post once I have the results. EDIT : (rephrased the paragraph above about the individual clocks)
As a clock input can be a combinatory term, my translation of the BDD example above can be simplified by completely removing the PIN definition for pin23 and it's .oe. PHI1 is now just a 'convenience' identifier, but the phrase
... will still correctly latch the bank data from the data bus on the falling edge of CLK. Tested in silicon/breadboard !
The second example is from a package of Atmel examples that target many different PLDs. This one is called EX375 but it shows how to create a 20-bit counter using some of the '750s features. Note the use of the '.ck', '.ckmux' and '.dfb' terms. (*) Properties of Quarks - elementary particles (quantum physics)
Whenever I've seen references to the ATF750 on the net it's nearly always called "a 22V10 on steroids". I suppose in some ways it's true, but I think it's rather 'cliché', as they say here in France
In this thread I'll document my discoveries about this unfortunate "black sheep" of the Atmel ATFxx series PLDs. Black Sheep for a major part in that very few PLD programmers actually know/care about it, probably due to some very wierd programming algorithms...I'll talk about a fairly affordable DIY and open source solution for the programming later-on. I'd like to talk about the Charm and strangeness first.
The Charm
The device's pin configuration is identical to the 22V10. The "750C" version is a 5v beast, but there is an "LVC" version which can be used at 5v or down to 3.0v. Even when used at 3v, the inputs are 5v tolerant - which makes the device quite useful for interfacing. The ATF750LVC is available as 24-pin DIP but also in PLCC, SOIC and TSSOP formats. I'm not sure, but AFAIK there is only one speed option for the LVC, the "-15", which is rated at 15nS maximum propagation delay (pin-to-pin) *AT 3V* (the datasheet says 10nS max. at 5v). So a good candidate for address space decoding, or for latching the extended address lines from a 65816 (see example 1).
From the outside the '750 looks like a 22V10 - but under the hood there's a much bigger motor...
- A complete macrocell (from <Using-ATF750C.pdf>)
Note that combinatory logic still has the same large fan-in (note the switch symbol between the two F/Fs) : each half has from 4 to 8 product terms, the two sides are then summed.
- Buried node numbers (from <Using-ATF750C.pdf>)
While talking about inputs and outputs, it's worth mentioning that the "polarity" of each pin (i.e. active high or active low) is defined in the PINS declaration. By default a pin is active high, to make it active low you simply place the '!' character in front of the pin name (e.g. !WR).
The next feature is that each F/F has it's own individual clock line with a selection switch to either use the 'master' clock (Pin1), or an internal signal, either a physical signal or a combinatory term. Each F/F clock can be either synchronous (by specifying '.ckmux'), or asynchronous (by specifying '.ck'). See the EX375 example, below.
And, to finish the list, each F/F has it's own Asynchronous Reset term, '.ar'.
The Strangeness
There were probably some compromises made in order to squeeze all this into the small package, the biggest and strangest of all is that the Synchronous Preset term '.sp' is GLOBAL - it affects ALL of the F/Fs. If you declare it, it will become global for all registers. WinCUPL also makes things stranger because it knows about this "feature" and will report an error if you declare more than one '.sp' term, but will all the same issue warnings for all the other used registers that don't have their sp term declared.
The rest of the strangeness is the programming algorithm, which seems to have been held "top secret" since the existence of the V750B GAL.
Very few affordable programmers are able to program the 750 series.
Programming
One affordable version, which is tailored very much to the Atmel series of GALs and SPLD devices, is the open-source afterburner project. The programmer itself is a board that plugs onto a standard Arduino controller, it holds a 24-pin ZIF socket and a programmable voltage source for the different Vpp voltages.
The Arduino does all of the actual programming stuff, and it is 'driven' by a simple command-line interface that is compatible with Win, Mac and linux. The project maintainer, Alexander Shniperson ("ole00"), has also designed some special carriers that fit onto the ZIF socket to allow programming of different package outlines. Full build and calibration details are provided, along with the gerber files to send to your favorite pcb manufacturer. The board is easy to assemble and has footprints for both through-hole and SMT components. You'll need a programming environment for the Arduino (the klunky IDE is OK for this).
A big note, though : if you want to program the ATF750 or the ATF1500 family you should choose an Arduino Mega 2560 controller : it has the memory capacity on-board to handle the large fusemaps of these devices. I have been using afterburner to program 8V16 and 22V10 devices for over a year, and have worked with Alexander to iron-out a few problems that were encountered with the ATF750. And it works !
I have attached the ATF750LVC datasheet and, more importantly, a very useful Atmel application note about using the '750s features.
Examples
The first example is a slightly modified form of one of BDD's POC experiments. In his design he was feeding the decoder with both PHI2 and PHI1 (antiphase), and at the same time was eliminating any clock assymetry - a requirement at high clock speeds. I'm currently "messing about" with a redesign of the RP6502 'picocomputer' (using a pi pico to 'drive' the 6502) to incorporate the 65816. I'm not running at breakneck speeds (yet) and as the pico is a 3v device I'm glad to have a cheap and simple PLD that works well at 3v. As it's the pico that supplies the PHI2 clock, I need to have an inverted clock to be able to latch the extended address from the data bus. The declaration in the WinCUPL PLD file is simple, and it works. I haven't yet measured the propagation delay nor experimented with other feedback paths to see what effect they have. I'll update this post once I have the results. EDIT : (rephrased the paragraph above about the individual clocks)
As a clock input can be a combinatory term, my translation of the BDD example above can be simplified by completely removing the PIN definition for pin23 and it's .oe. PHI1 is now just a 'convenience' identifier, but the phrase
Code: Select all
[A18..A16].ck = PHI1;The second example is from a package of Atmel examples that target many different PLDs. This one is called EX375 but it shows how to create a 20-bit counter using some of the '750s features. Note the use of the '.ck', '.ckmux' and '.dfb' terms. (*) Properties of Quarks - elementary particles (quantum physics)