65C22 Shift Register - Some Guidance, Please?

[DRG]

I'm attempting to understand the 65c22's shift register. In order to do so, I've written a small program to send $0F then $F0 in an endless loop through mode "110" (shift out under PHI2 clock control). However, the output (as seen on my logic analyser) isn't what I expected. I've attached both my code and the output as my understanding of the initialisation and handling of interrupt bits is probably deficient despite reading through the datasheet as best I can.

Firstly, am I right to say Fig 2.13.3 should refer to "CB2 OUTPUT DATA" and not "CB2 INPUT DATA"?

My code is here...

Code: Select all

; sr_test.a65
; Send $0F and $F0 to shift register in infinite loop.
;

; ******************************************************************************
; Define VIA 65C22 address lines.
; ******************************************************************************
SR 	             = $600A                       ; Shift Register.
ACR 	            = $600B                       ; Auxillary Control Register.
PCR 	            = $600C                       ; Peripheral control Register.
IFR 	            = $600D                       ; Interrupt Flag Register.
IER 	            = $600E                       ; Interrupt Enable Register.

; ******************************************************************************
; Bit manipulation values. 
; ******************************************************************************
SBIT0	            = %00000001
SBIT1	            = %00000010
SBIT2	            = %00000100
SBIT3	            = %00001000
SBIT4	            = %00010000
SBIT5	            = %00100000
SBIT6	            = %01000000
SBIT7	            = %10000000
CBIT0	            = %11111110
CBIT1	            = %11111101  
CBIT2	            = %11111011
CBIT3	            = %11110111
CBIT4	            = %11101111
CBIT5	            = %11011111
CBIT6	            = %10111111
CBIT7	            = %01111111


; Programme start.	
	.org $0400

; Code goes here...
app_start:
        lda ACR                             ; Get current value of Auxillary Control Register.
        and #CBIT2                          ; Clear bit 2.
        ora #(SBIT4 | SBIT3)                ; Set bits 4 & 3.
        sta ACR                             ; Store new value in Auxillary Control Register.

loop:
        lda #$0F
        sta SR                              ; Write to shift register.
        lda IFR
        and #CBIT2
        sta IFR                             ; Clear IFR2.
        lda #$F0
        sta SR                              ; Write to shift register.
        lda IFR
        and #CBIT2
        sta IFR
        bra loop

; Return to the monitor.
        rts

Using Fig 2.13.3 to compare PHI2 & CB1 - they look as I'd expect. But my interpretation of the output is that I can only see $0F being outputted. I've shown why I think this.

Any ideas as to what I'm doing wrong?

Thanks.

Dave

EDIT
Still tinkering, I tried just...

Code: Select all

loop:
        lda #$0F
        sta SR                              ; Write to shift register.
        lda #$F0
        sta SR                              ; Write to shift register.
        bra loop

And the output is better...

pulseview2.png (10.99 KiB) Viewed 3715 times

[GARTHWILSON]

DRG wrote:

Firstly, am I right to say Fig 2.13.3 should refer to "CB2 OUTPUT DATA" and not "CB2 INPUT DATA"?

Yes, output.

Remember that under control of phase 2, each phase-2 cycle toggles (not cycles) the CB1 clock, meaning that a whole byte requires 16 phase-2 cycles.  Without trying it now, I suspect the problem is that you're writing to the SR while it's still busy, and the new byte gets ignored.

If you don't have the interrupt enabled, you can disregard the SR interrupt flag bit.  Edit: You could read the flag to see when the SR is ready for another byte; you don't have to explicitly clear the flag though, as that's done automatically by reading or writing the SR.

[hjalfi]

Quote:

I suspect the problem is that you're writing to the SR while it's still busy, and the new byte gets ignored.

Is there a way to reset the shift register and start a new byte before the old byte has completely shifted out? (I thought that writing to SR would do this, but it seems not to.)

[GARTHWILSON]

I don't know, but you could try changing the SR mode before the byte is finished.