Why does Hanson's diagram show PCH increment as 2x4bit?
Posted: Thu Jan 23, 2025 2:45 am
Hanson's diagram for reference: https://www.weihenstephan.org/~michaste ... 2/6502.jpg
The program counter is shown as two 8-bit registers. This makes sense because the internal architecture treats them as two separate registers, addresses need to go through the ALU in 8-bit units.
However, Program Counter High Select and its increment logic are shown as being further split into two 4-bit segments and I cannot figure out what feature of the processor needs this, or even what on the diagram could interact with this. The only extra signal gained here is the half carry (PCHC), but I cannot find this going anywhere else in the diagram.
Is there an architectural meaning to this split, or is there another reason this showed up on the diagram?
The program counter is shown as two 8-bit registers. This makes sense because the internal architecture treats them as two separate registers, addresses need to go through the ALU in 8-bit units.
However, Program Counter High Select and its increment logic are shown as being further split into two 4-bit segments and I cannot figure out what feature of the processor needs this, or even what on the diagram could interact with this. The only extra signal gained here is the half carry (PCHC), but I cannot find this going anywhere else in the diagram.
Is there an architectural meaning to this split, or is there another reason this showed up on the diagram?