Why does Hanson's diagram show PCH increment as 2x4bit?

[Jefffrey]

Hanson's diagram for reference: https://www.weihenstephan.org/~michaste ... 2/6502.jpg

The program counter is shown as two 8-bit registers. This makes sense because the internal architecture treats them as two separate registers, addresses need to go through the ALU in 8-bit units.

However, Program Counter High Select and its increment logic are shown as being further split into two 4-bit segments and I cannot figure out what feature of the processor needs this, or even what on the diagram could interact with this. The only extra signal gained here is the half carry (PCHC), but I cannot find this going anywhere else in the diagram.

Is there an architectural meaning to this split, or is there another reason this showed up on the diagram?

[BigEd]

It's an implementation detail: there's a carry look ahead (or indeed, carry skip) so the top 4 bits doesn't have to wait for the next lower four. See for example
https://retrocomputing.stackexchange.co ... ncrementer

(Also mentioned previously... see these threads for more interesting discussion of implementation)
viewtopic.php?p=41205#p41205
viewtopic.php?p=57084#p57084
viewtopic.php?p=89277#p89277

[Jefffrey]

Oh, that's surprisingly straightforward, thank you very much for your help!

Also thank you for helping me out back in 2015. Not sure why I disappeared, but the information was useful then, and it was useful last week when it came up in search results

[BigEd]

Welcome back! I do like it when search results give us helpful posts from the past!