Parallel Interface ports on 65c265SXB

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ccureau
Posts: 33
Joined: 02 Apr 2003

Parallel Interface ports on 65c265SXB

Post by ccureau »

I'm wanting to use the 265SXB that I've bought for something more useful than blinking LEDs, and so I've decided to build a floppy controller from it.

Background: My son and I both acquired Kaypro IIs, and no way to write new disks. If I had an older DOS machine it would be simple, but eBay sellers want gold for old machines nowadays. So I found a IBM-labelled MPI DS DD 5.25" drive. Now I just need a way to read and write disks. And, if the C1541 could do it with a CPU and VIA, I should certainly be able to do it with a MCU with ports. Yes, I know that this has already been done both with the Arduino and Raspberry Pi, along with many other projects. But if I wanted a simple way to do it, I wouldn't own a 265SXB, would I? :D

Finally, to the question! From the memory map, I can see what looks like a CIA split across 00:DF00-00:DF07 and 00:DF20-00:DF27, which should give me 8 ports to bit-bang with. Unfortunately, this isn't enough for all of the signals I need to send or read from the floppy controller. I do see a parallel interface at 00:DF78-00:DF7F that might be able to be used, but I've got no information on how these ports might work or if I could use them in this way. I see that they can manage interrupts, which I won't need to use.

Has someone teased out all of the available ports from these chips? Documentation, as has been said many times before, is really terrible...
ccureau
Posts: 33
Joined: 02 Apr 2003

Re: Parallel Interface ports on 65c265SXB

Post by ccureau »

Okay, I've done a bit more study of the datasheets for the 265sxb and the '265 itself. I can see that J4 and J5 are the UARTs (when enabled) and just plain pins (P50-P57, P60-P67) when disabled.) If I keep these pins disabled, including the special interrupt functions for P56, P60, and P62, can these lines be used as GPIO pins? If so, is there some instruction on how to do this?

EDIT: and of course I find these paragraphs after my post...
Quote:
3.9 I/O Port Pins (Pxx)
All ports, except Port 7, which is an output Port, are bi directional I/O ports. Each of these bi-directional
Ports has a port data register (PDx) and port data direction register (PDDx). A zero ("0") in PDDxx
defines the associated I/O pin as an input with the output transistors in the "off" high impedance state. A
one ("1") in PDDxx defines the I/O pin as an output. A read of PDx always "reads" the pin. After reset, all
Port pins become input pins with both the data and data direction registers reset to 0.
Port 7 has a Chip Select register (PCS) that is used to enable Chip Selects (CSxB). A "1" in bit x of PCSx
enables Chip Select CSx- to be output over P7x while a "0" in PCSx specifies the value in the output
data register is to be output on P7x. Port 7 data register is set to all "1's" after Reset, and PCS is cleared
to all "0's" after Reset.
I read this to mean that even if the UARTs are disabled I can still use the pins as I/O, except pin 7 which is output only. Time to hook up the logic analyzer and get some sample code together :)
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