Read/Write to MOS6550 RAM

[gmc]

I'm trying to build a Arduino based project to read/write to MOS6550 RAM (1024 x 4 bit)

Datasheet is here:
https://www.zimmers.net/anonftp/pub/cbm ... asheet.pdf

Looking at the datasheet there is sparse information on exactly what timing are needed and the logic. Read/Write waveforms would have been nice.

Quote:

6550 cycle operation is controlled by the PHI2 clock. Addresses are presented to the address pin then PHI2 is low and are latched on chip to the rising edge of the PHI2 clock
The 6550 outputs are in a high impedance state whenever the memory is de-deselected, PHI2 clock is LOW, or R/W is LOW

I am trying to interpret this and don't think I have the logic right.

Writing:
PHI2 LOW, RW LOW, Chip Selected
Set Address pins
Set Data pins
PHI2 HIGH


Reading:
PHI2 LOW, RW HIGH, Chip Selected
Set Address pins
Set Data pins
PHI2 HIGH

Does this look correct? Is there a better datasheet available containing timing diagrams?

[leepivonka]

Looking at the (very minimal!) datasheet, this was designed to connect to a 6502 bus, so you want to simulate how a 6502 does the accesses.

The datasheet doesn't say, but I wonder if there are some dynamic nodes that will lose their state if the part is cycled very slowly, or even if PHI2 is cycled too slowly (a 6502 system runs PHI2 continuously).

I think you're essentially correct. I've added some detail below, including waits:

---Initialize---
PHI2 lo (not in an access)
Chip deselected

---Reading---
assume PHI2 was lo
assume Chip was deselected
Set address pins
Set data pins to input
RW hi
Chip selected
Wait >200nm (address setup time)
PHI2 hi (latch address & start access)
Wait >400ns (data access time)
Read value from data pins
PHI2 lo (end the access)
Chip deselected

---Writing---
assume PHI2 was lo
assume Chip was deselected
Set address pins
Set data pins to output with the desired data
RW lo
Chip selected
Wait >200ns (address setup time)
PHI2 hi (latch address & start access)
Wait >400ns (data write time)
PHI2 lo (end the access)
Chip deselected