Basic questions on patching into a 6502 on apple motherboard

[paritybit]

Hello all!

I think have a very basic question. I'd like to know what concerns I might have trying to patch directly into a 6502 on an apple IIc motherboard.

Basically what I want to try is to sandwich a PCB between the mobo and CPU where I can then use the PCB to fool with the processor pins. I'm looking to build interface logic between a raspberry pi pico and the running processor.

I think my question really is about how much TTL load can I expect to hang off the processor without causing problems.

I realize that between 6502 and pico I need level shifters. I'm thinking that between the address bus, data bus, and a few other pins like R/W, etc. I'm likely to just hang 1 load off of each pin like a 74LVC245 and then everything else from there is 3.3v stuff. What I don't really have a sense for is how much other load the IIc mobo puts on the processor and if what I want to do is OK.

What am I doing with this? Unknown just yet but I have 2 experiments in mind to get me thinking. The first is some kind of passive address/data and r/w sniffer that can sense when certain addresses are hit and record their I/O. The other is some method to interrupt the CPU and then do DMA like transfers in and out of RAM directly.

I'm still thinking about this and what's the safest way to start without frying my equipment.

I have some existing basic equipment to start like volt meter, soldering station, old tektronix T922 to play with. Mostly been in software including 6502 assembly way back in the '80 and kind of looking to play with that and some hardware again.

Thanks!

[GARTHWILSON]

Welcome.

The IIc had the CMOS 65c02 processor, right?  Its outputs were much, much stronger than the NMOS 6502's.  If your loads are all CMOS, and they're right there at the processor's pins with very little lead length, I'm sure you don't have anything to worry about.  I have summarized the many differences between the NMOS and CMOS versions at http://wilsonminesco.com/NMOS-CMOSdif/ .

[paritybit]

Yes the IIc has the 65c02. I think also the platinum IIe, maybe the enhanced IIe as well. But IIc is what I'm targeting for this.

If I need to start with breadboard for initial prototype, how long of jumpers can I reasonably use from the mobo/processor to my experiment board?

Although I might like to target a hardware project to the older apple II's, those other machines have slots with pins that are buffered -- so I don't think there's much need to interface with the processor directly.

Thanks!

[GARTHWILSON]

paritybit wrote:

how long of jumpers can I reasonably use from the mobo/processor to my experiment board?

I assume the processor is rated for maybe 2MHz or 4MHz, not 14.  (The modern 65c02's are rated for 14MHz but a couple users have gotten them up to around 40MHz.) I'm sure you'll do fine with connections several inches long.  Don't run them a foot or more over to something beside the IIc on the workbench though.  What runs the risk of trouble with long connections is not the MHz, but that the parts that can go faster have fast transitions, measured in nanoseconds.  See the applicable page of the 6502 primer at http://wilsonminesco.com/6502primer/construction.html .  It will give considerations most hobbyists have not thought of, things that can bite you but are easy to avoid if you have a little understanding of what goes on with these fast rise and fall times.

[paritybit]

Thanks much! I should have noted, the IIc runs at 1mhz. I'm probably not up to trying to figure out how to overclock that given various limitations on the soldered in ram/rom chips. But once I get to running some DMA related tests I might try to supply my own clock to the CPU so I can slow it and speed it up as needed for fun and debugging.

Thank you.