65C22S in NMOS design

[brain]

For space reasons, I would like to use a QFP-ish package for the 65C22 for a Commodore 1541 hardware enhancement. As many know, the NMOS-compatible 65C22N is not available in such a package, but only as PLCC and DIP.

I know about the IRQ line difference and how that can be addressed with a diode, but the rest of the differences I am less sure about:

* I see the -S has bus holding on most IO pins. Would that cause issues if used in an NMOS design?
* Obviously, the Vih is 4V as opposed to 2V. I know I need to check all input lines of the VIA for any issue,s but is there more I need to check?

Jim

[GARTHWILSON]

I can't see the bus-holding devices doing anything but good. It's a simple but ingenious design.

For inputs, you might need pull-ups, either passive (resistor) or active (current-mirror, which is faster without undue loading) to get valid logic-1 states from NMOS or LSTTL outputs. If the data sheet I'm looking at is valid, the 22N has, more or less, 74LS-type input loads on the port pins. The 22S has true CMOS inputs whose only input current is just the negligible CMOS input leakage, something that can be very important for some applications.

According to my experiments, the S version of the '22 has very strong outputs—much, much stronger than the data sheet lets on. I doubt that would cause any problems though.

[brain]

I wonder if passive pullups on the CMOS part would be fast enough on a 1-2MHz application... Current mirrors would be nicer, but could add significantly to the parts quantity and/or board real estate.

Jim

[GARTHWILSON]

I expect there would be no problem, but I would have to experiment. It will come up fast to about 2.5V, a little slower to NMOS's and 74LS's maximum output voltage of what, maybe 3.5V?, and most slowly beyond that. IOW, a passive pull-up is not working alone until the voltage gets to about 1.5V below Vcc, and in fact is only really needed to finish up the job. (You already knew that though.)

[BigEd]

Are we talking about converters on the '22s interface to the micro, or the external-facing interface?

Either way, level shifting ICs are readily available, which handle 8 (or more) signals in one chip.

[Dr Jefyll]

A PLCC is pretty compact, so it strikes me there's not much space saving by going to a QFP instead. But that's for you to judge.

Just remember that use of the -S part has different implications for the Port A and Port B lines than it does for the lines of the Bus Interface.

In all cases the -S part's bus-hold feature will tend to weakly pull a high-ish line all the way high, and tend to weakly pull a low-ish line all the way low. For the bus lines I don't see that creating a problem. But the 1541 circuitry may rely on the assumption (valid for -N and vintage VIA's) that port lines which are configured as inputs will invariably try to pull themselves high (and thus can be driven by an open-collector gate or by a switch to ground). Dunno if that applies to 1541, but you'll definitely need external pullups for any port input lines that rely on that assumption.

-- Jeff

[brain]

GARTHWILSON wrote:

I expect there would be no problem, but I would have to experiment. It will come up fast to about 2.5V, a little slower to NMOS's and 74LS's maximum output voltage of what, maybe 3.5V?, and most slowly beyond that. IOW, a passive pull-up is not working alone until the voltage gets to about 1.5V below Vcc, and in fact is only really needed to finish up the job. (You already knew that though.)

Yes, just wondering on the last .5V to get it to 4V and the time in the effective RC curve needed to do so.

Jim

[brain]

BigEd wrote:

Are we talking about converters on the '22s interface to the micro, or the external-facing interface?

Either way, level shifting ICs are readily available, which handle 8 (or more) signals in one chip.

Not sure I understand your terminology, but the application would be a small PCB that plugs in where the NMOS 6522 fits in the 1541. As such, all pins that are defines as inputs (RESET, PHI, PORTA, PORTB, etc.) would need some help to ensure a high level is 4V, not just 2V as specified by the NMOS 6522 and the 65C22N

As I noted for current mirrors, level shifters are nice...

Quote:

but could add significantly to the parts quantity and/or board real estate.

Which is my main concern. In this application, I may need to put a small CPLD, a 65C22S, a 75160, and a 75161. And, all of it needs to fit in the DIP40 footprint. Putting passive level shifters on PORTA, PORTB, and all the ancillary input lines like PHI, RESET, and C*[12] lines that need it would be 3 addition TSSOP20s, at least. I don't think all of that will fit on a 40 pin footprint.

Jim

[brain]

Dr Jefyll wrote:

A PLCC is pretty compact, so it strikes me there's not much space saving by going to a QFP instead. But that's for you to judge.

Just remember that use of the -S part has different implications for the Port A and Port B lines than it does for the lines of the Bus Interface.

In all cases the -S part's bus-hold feature will tend to weakly pull a high-ish line all the way high, and tend to weakly pull a low-ish line all the way low. For the bus lines I don't see that creating a problem. But the 1541 circuitry may rely on the assumption (valid for -N and vintage VIA's) that port lines which are configured as inputs will invariably try to pull themselves high (and thus can be driven by an open-collector gate or by a switch to ground). Dunno if that applies to 1541, but you'll definitely need external pullups for any port input lines that rely on that assumption.

-- Jeff

The 1541-II, for example, has literally just enough room for the 6522 to sit below the drive mech. By the time you put a header and a .8mm PCB together, I appear to have less than a PLCC44's worth of height before hitting the drive mech. QFP will work, and might even be possible to place on the bottom of the .8mm PCB, in between the header rows. I know for a fact the PLCC44 would not fit between the rows.

And, as for pullups, that was my first thought, but I am concerned about rise time.