Video sync ICs

[Dan Moos]

I'm working on VGA compatible video for my build. I have a slightly buggy version gong now, that is built from all 7400 logic. The character ROM and dual ported RAM chip are the only exceptions.

As you can imagine, this requires a ridiculous number of counters, magnitude comparitors, flip flops, ect. I have the sync generation and character generator on a PCB, the rest still on breadboard. That PCB is twice as large as the actual computer PCB.

Now that I've proven to myself that I can do this the hard way, I'm interested in a simpler method. I think I could get the chip count to a reasonable level if the sync signals could be generated by a single chip.
I'm sure such a thing exists, but apparently I don't know what to search in Mouser.

I know I can do this with a microcontroller, and I actually already use an AT128 for keyboard. That chip is currently massively under utilized, so that is an option for sure.

I'm just curious what parts exist specifically for this. Anything from a simple sync pulse generator (best option), to something more capable. Not totally against obsolete parts, but would prefer not to use something difficult to acquire.

Have briefly considered FPGAs, and this would probably be a pretty simple project to dip one's feet into that world, but let's leave that alone for now.

[Dr Jefyll]

Dan Moos wrote:

I think I could get the chip count to a reasonable level if the sync signals could be generated by a single chip.
I'm sure such a thing exists, but apparently I don't know what to search in Mouser.

FWIW, in my experience Digikey's search is superior to any other I've used. I routinely search there, even if I plan to buy elsewhere.

I'm not so sure the chip you want exists, but it's worth looking, I suppose. If I were attempting to generate VGA sync signals with 74xx I'd probably consider 74HC4040 and its siblings -- many-stage ripple counters in a 16-pin package. Is it just one VGA format you're targeting (800 by 600, 60 Hz, for example)? What are the numbers you need to divide?

-- Jeff

[BigEd]

It might help if you always arrange to be counting down: parallel load a value into a counter, and detect zero (or underflow.) It might be that you can cascade small-value counters in which case maybe you could reuse some of the small values.

[Dan Moos]

I should re-clarify. My 7400 logic version is 90% operational. What bugs there are are simple ones I expect to have solved easily.

I'm wanting to explore simpler solutions. I know it can be done with a micro controller fairly easily, and I know it can be done with an FPGA.

I want to explore the possibility of ready made chips, if they even exist.

[BigEd]

Ah, so you want something like a 6845 or 6847 CRT Controller (CRTC) chip? Or an hd63484 ACRTC or maybe a TMS9918 Video Display Controller (VDC)? (I suspect all of these are no longer in production.)

Maybe some info can be gleaned here: http://www.vgamuseum.info/

Edit: this datasheet
https://www.bg-electronics.de/datenblae ... 90C61A.pdf
might give a clue:

Quote:

The Integrated Circuit Systems ICS90C61A is a dual clock generator for VGA applications. It simultaneously generates two clocks. One clock is for the video memory, and the other is the video dot clock

because it mentions

Quote:

Dual Clock generator for the IBM-compatible Western Digital Imaging Video Graphics Array (VGA) LSI devices, and 8514/A chip sets

[Dr Jefyll]

I suspect ready made chips will be large (40 pin?) devices with a LOT more functionality than just the sync generation you're asking for. Maybe that's OK.

If not, and you still want an alternative to a microcontroller or FPGA (actually a CPLD would do), then you could consider a state machine built with an EPROM plus a '574 and probably two or three other 74xx chips. Retrieving stuff from ROM makes it easy to accommodate intricate sequences and counts that aren't powers of two. I haven't fleshed out this idea, but if you detail the requirements I'm willing to see how it pans out. (ps: I guess it won't save any space, compared to a 40-pin!)

-- Jeff

[Rob Finch]

VGA supports a lot of different formats and many displays are fairly flexible to timing. Could you use just a couple of one-shot multivbrators (74LS123) to generate sync signals? This is the non-recommended way to generate sync, but it's only one chip. There would still be a need to count off when to display data.

[Agumander]

Wouldn't there be overlap between the chips used for generating sync and the chips used for generating the address into video memory? It might not actually save as many chips as you expect.

[Rob Finch]

Another way to generate sync signals would be to use something like an 8254 or 6840 counter chip. It would need a pre-scalar to lower the input frequency to something the 8254 or 6840 can count. Has the advantage of allowing the sync shape to be programmable. A DMA controller could then be used to generate addresses and fetch lines for the display.

I like BigEd’s suggestion of the 6845. It has programmable timing and address generation in one chip. It’s not really meant for VGA but is easy to adapt, additional address bits must be generated by pre-scaling the dot clock input to the chip. It may not be possible to use this chip for a linearly addressed display, but with tiles.

[Dr Jefyll]

For generating sync pulses or other repetitive waveforms, a notion I find promising is to use the bitstream regurgitated by an SPI-based EEPROM. Used for HSync and VSync, the circuit would behave like a pair of counter/dividers but in fact it's based entirely on the recall of stored information.

My first pass on the idea (not shown) was a mild case of overkill, although it'd be a good solution for a more complex problem. I'll describe the idea briefly in this paragraph, then move on to a simpler solution. The first pass design used a single SPI EEPROM whose serial output fed a 'HC4015 shift register whose parallel outputs drove a 74_259 octal addressable latch. An extended serial string of zeros would be NOP -- no change. Action results only when the bitstream encounters 5-bit commands in the form of a Start Bit and 4 data bits, with the latter interpreted as 1-bit data and 3-bit address for a write to the '259 output register. So, the command could say things like, "Set the '259 pin that's designated as VSync," or reset it, or set or reset the HSync output instead... Highly flexible, really. The '259 gives you eight outputs to play with, so you'd have quite the little sequencer, and with only a handful of chips! Schematic available on request. But if you only need two outputs there's a simpler way.

Subsequent doodling (below) slashed the chip count even further, despite doubling the EEPROM count to two. (These 8-pin EEPROMs are pretty darn small anyway -- also quite affordable.) As you can see, the bitstream is used as-is, without any encoding (except that the falling edge of VSync is used as a signal to restart the regurgitation).

In order to start (or restart) regurgitation, the EEPROM needs to be sent an 8-bit Read opcode followed by a 24-bit Start Address, and generating that 32-bit sequence would be unduly bothersome if you want the start address to be zero. But it just so happens that a Read opcode followed by a start address of $FFFFFF is easy to generate, and that's what I've configured the '164 shift register to do.

Following reset or restart the '164 sends the EEPROM a sequence which is just a single low-to-high transition (this is the waveform applied to the D input, as shown in the timing diagram). As you can see, /CS falls and stays low, and six clocks later D rises and stays high. The framing is such that the EEPROM sees the string as opcode $03 (a Read command) followed by the first address that'll be read: $FFFFFF.

I'm pleased with how lean the design is.... Maybe someone can put this idea (or the 259-based sequencer) to use...

-- Jeff

Edit: improved text, and an update. Some while ago I built the circuit and was happy to find the idea successful. The only thing that bothered me was the active-low pulse applied to /CLR, whose duration needs to be controlled in order to keep the '164 clear for a predictable number of cycles. I didn't trust the simple RC shown in the schematic above, so here's how I trimmed the pulse width in order to keep the '164 clear for exactly one cycle.

[BigEd]

Ingenious!