6502.org

I mentioned in another topic that I was building a retro 6502 computer. BigEd suggested I share, so here goes.

I am in the process of bootstrapping a modular 6502 system built around the open source Z50 bus. So far I have assembled a third party backplane and designed several boards to plug into it, currently CPU, memory, serial and prototype boards. Boards are either 100x100mm, CPU and prototype, or 100x75mm, serial and memory.

The CPU card contains a WDC65C02 processor, clock generator (1MHz), address and data bus buffers and an ATF22V10 GAL for utility and memory decode. The original design was for NMOS, hence the buffers, but it turns out the second hand chips I obtained from China were all defective in various ways. After a several frustrating debug sessions I decided to buy a couple of new processors. It paid off, the board worked almost immediately. I say almost as I hadn't realised the BE and VPB mods in the new model.

The memory board is designed for 2 x 32k SRAMs and 1 x 32k ROM. I've made the design quite flexible, the memory map is configurable using DIP switches. You get to choose your RAM/ROM sizes - 32/32, 40/24, 48/16 or 56/8. I am using a second GAL, an ATF16V8, for the chip select function.

The serial card has a single 6551 type chip. Because of the Chinese chips problems I decided to get a WDC65C51, not realising it has its own issues. I intend to proceed with the NMOS for now and see how it pans out.

One of the prototype cards has been set up as a static debug board. I've taken the Mostek example circuit from the hardware manual (pg. 125) and put it into an old Xilinx XC9536 CPLD. I happened to have a few lying around from a previous project and they are both 5V powered and 5V tolerant. It's very much a work in progress but the halt/run/single step operates properly. What is missing is an address/data bus display.

Toolwise I am using the cc65 project, just the assembler and linker portions for now. I'm happily building test ROM's from the command line using Gnu make.

Best I can tell the CPU and ROM are working properly. I've based my memory map on the Apple ][, so RAM 0000-7FFF, IO C000-CFFF and ROM E000-FFFF. The first test ROM just has the reset vector jump to F800 and then access a bunch of IO memory locations in a tight loop. From what I can see on the 'scope it's running true and generating the expected memory enable signals.

This weekend my plan is to add the serial card to the mix and try for "Hello world". Once that is working I'll aim at a workable console so I can start on RAM testing and then on to a basic ROM monitor.

All good fun.

Great to see another 6502 project going. Welcome!

Cheers,

-Gordon

That's great to see!

Those are nice looking boards. I especially like the DIP switch reference on the silk screen.

Welcome, SteveD! Thanks for dropping in.

Hey, I see you just posted about ordering a WDC cpu from Mouser. And earlier you mentioned creating your own version of the Stop-Step circuitry published in the original MOS manuals from the 70's. Just a reminder, the 21st century WDC product is such that the RDY input can extend read cycles and write cycles. (The original NMOS chips couldn't extend writes, only reads.) Hence you may wish to or be forced to alter the Stop-Step circuitry used. Cheers,

Jeff

@Jeff, Thanks for bringing that up. Can't say I understand the write cycle part of the step-stop circuit, have just implemented it as given. Haven't read much of the 65C02 data sheet yet. Last time I seriously wrote 6502 assembler was back in the early 80's, so I'm just a little rusty . Am looking forward to the new instructions. The bit set/reset stuff makes me wonder if I should put some IO on page zero.

Progressed the computer to the "Hello world" stage today i.e. serial port console. Based on forum discussions re WDC65C51 issues I decided to try out a Rockwell 6551 pull. Guess I got lucky, it worked first time.

Project status is:
1 - modified Rev A CPU board running with WDC65C02 @1MHz (plus ATF22V10C)
2 - unmodified Rev A memory board running 8k ROM E000-FFFF (plus ATF16V8)
3 - unmodified Rev A serial board running with Rockwell 6551

Next step is to code up a RAM test routine. Am assuming that RAM is not working so am coding without ZP and a stack/subroutines for now.

If you first test ZP, and prove that it does work, then you can use it as a springboard to test the rest.

Well, I wouldn't bother with that circuit, myself -- it's needlessly complex. It accommodates the old NMOS parts, which don't allow stopping the clock. But on the new CMOS parts you can stop the clock. Also the circuit features the ability to step one instruction at a time, which is nice but not really necessary. All you really need is the ability to step one clock cycle at a time.
I think you will appreciate the C02's new instructions a LOT!
Been there, done that, and you and I are in agreement. Depending on priorities and circumstances, IO in zero page can be a great idea! But some 6502.org forum members reject the idea unconditionally.

The WDC65C51 bug is interrupt related, and I'm guessing you don't use interrupts yet. (It's kinda hard to use interrupts when you don't have a stack! )

-- Jeff

Managed to port the open source Micromon to my computer (a BIG thanks floobydust) and got it all working. The only hiccup was not setting the 6551 /DCD signal correctly. Once the driver input was tied high everything worked.

Guess I need to think of something to make it do now

Actually, the Xmit bug is worse... as the bit in the status register is stuck on, you can't use polled mode I/O either, as it always looks like it's ready to accept a new character to Xmit.
Glad you got it working! You might want to take a look the SBC-1... the BIOS and Monitor there are more full featured.... also supports a 6522 for timers and ports. It is larger, but does a LOT more.