Indirect Addressing (JMP)

[andrewem]

I came across the chart below in a 6502 manual for the Indirect Addressing mode (JMP instruction).

The problem with the chart is that it does not specify where the data goes. For example, on cycle 2, where does it put the AAL so that it doesn't get overwritten by the AAH on cycle 3?

Please help.

Andrew

--- CHART ---

CYCLE # | ADDRESS BUS | DATA BUS
1 | PC | OpCode
2 | PC + 1 | AAL
3 | PC + 2 | AAH
4 | PC + 2 | AAH
5 | 0,AA | New PCL
6 | 0,AA | New PCH

PC = Program Counter
AA = Absolute Address
AAL = Low-byte of Absolute Address
AAH = High-byte of Absolute Address
PCL = Low-byte of Program Counter
PCH = High-byte of Program Counter

[GARTHWILSON]

WDC's simplified internal architecture block diagram just calls it an "input data latch" (DL register).

For future reference, in order to avoid losing the extra spaces in your diagram so you can preserve the vertical alignment, uncheck the "Disable BBCode in this post" box under the window where you're writing, and mark the block and click "Code" above the window. You can still go back and edit your post later too.

[andrewem]

GARTHWILSON wrote:

WDC's simplified internal architecture block diagram just calls it an "input data latch" (DL register).

So does this mean that on cycle 3, the Address Bus contains AAH and the Input Data Latch contains the AAL?

[GARTHWILSON]

On the third cycle, the address bus has the address of the third byte of the 3-byte JMP instruction.

The diagram shows this DL with connections to both the internal ADL and the internal ADH, so it probably has two 8-bit halves. From a programming standpoint, what matters is what each instruction does and how many clocks it takes-- not necessarily how it does it internally. Some of the internal pipelining is interesting to see how the processor can do several operations in one clock so each instruction takes very few clocks; but that information is not essential to doing a good job of programming. It would be more useful if you're trying to write VHDL or Verilog code to make your own processor with an FPGA.

[andrewem]

I'm asking because I'm working on an 6502 emulator and you're right that although I don't need to know what the chip's doing with the byte that's on the Data Bus (I can store it in a variable), I am interested in understanding what the chip itself does with the previous byte on the Data Bus - I mean it must store it somewhere? Otherwise how can it join the AAH and AAL together to create the resulting 16-bit address?

Andrew

[GARTHWILSON]

You would do well to get WDC's programming manual. It's kind of expensive at $60 or so, but indispensable for anyone serious at this game. Their data sheets also give some cycle-by-cycle information. If you make your buses reflect the same thing as the actual processor's buses, I suppose how you do it internally wouldn't matter much although it would probably end up being similar to how Bill Mench (the designer) did it. WDC's website is www.westerndesigncenter.com .