Another My-First 6502 project :)

[Briggs]

Hi,

first post here after a lot of reading. First of all I would like to thank all of you for all information on this site. I have read to many articles and forum posts to remember them all but thank you all!

I got bitten by the 6502 bug about 2 months ago and have recently been able to do a sort of freerun with it, anyhow I thought I would post some of my thoughts here and maybe get some feedback

First the memorymap, this was really hard to wrap my head around in the beginning but Garth´s primer and all questions about it and certainly helped. So I settled for the following, almost 32kb ram and 32 kb rom and 8 i/o possibilities (yeah i know, lots of i/o but I really do not like holes in my memorymap ).

Ram $0000-$77FF
i/o 1 $7800-$78FF
i/o 2 $7900-$79FF
i/o 3 $7A00-$7aFF
i/o 4 $7B00-$7bFF
i/o 5 $7C00-$7CFF
i/o 6 $7D00-$7DFF
i/o 7 $7E00-$7EFF
i/o 8 $7F00-$7FFF
Rom $8000-$FFFF

The schema for this (oh and btw I can really recommend Logisim) goes like this, which should be enough for 1 MHz. Appologies for the poor picture quality (mobile phone).

Anyhow, now I have tried to do a freerun with nop instructions hardcoded (going the route everyone else has). Problem is that I only have a multimeter as my only instrument so I thought to use Garth´s singlestep logic and a simple reset trigger. At first nothing seemed to work then I realised I had to tie the Bus Enable pin high. Actually at first I connected the 5+ to the Vector Pull Pin but uhm yeah we will forget about that Anyhow, to make along story short, I did not get the singlestep circuit to work but when running the 6502 with my 1MHz Oscillator it seems to work since all the adress pins are at 2.5Volt which seems to indicate that they are switching between 5 and 0 Volt.

So my next step is to connect my EEPROM (I took a shortcut and ordered a programmer from ebay) to the 6502 and program it with a infinite loop just to be able to measure that the correct pins are lit.

Any comments or criscism are welcome, oh and btw here is a link to my weblog which unfortunately is in Swedish http://monobit.se/mua/

Thanks again
Jan Svensson

[floobydust]

First, welcome to the the forum!

Seems your basic memory map is fine, but you are allocating 2KB of addressing to your I/O devices. Any particular reason for something this large? What I/O devices are you planning on using once you get the board up and running? My small CPU board has 8-I/O selects, but I only use a single page for I/O which allows each select to be 32 bytes wide. You can also take a look at Daryl's SBC-2 board/schematic linked here:

http://sbc.rictor.org/sch2.html

Using a single page (256 bytes) will save you more memory and still give you ample addressing space for I/O devices. As a side note, I'm using 74HC logic for my board (74HC00, 74HC30, 74HC138) and have been running at 10MHz for almost two years without any issue.

[GARTHWILSON]

64KB of memory space is absolutely huge for a beginner to fill; so I'd say you're not in any danger of running short. Fine-grained address-decoding schemes will however usually require greater logic delays, reducing your maximum operating speed. It will also take more board space (unless you use programmable logic). To keep the logic ultra simple (and to run considerably faster than the parts are rated for), I left 16KB for I/O on my workbench computer. I've been using it regularly for 20+ years, and the only thing I've ever needed more memory for is data arrays, never code. Daryl does offer a pre-programmed programmable logic IC for fine-grained address decoding though, at http://sbc.rictor.org/decoder.html .

[Briggs]

floobydust wrote:

First, welcome to the the forum!

Seems your basic memory map is fine, but you are allocating 2KB of addressing to your I/O devices. Any particular reason for something this large? What I/O devices are you planning on using once you get the board up and running? My small CPU board has 8-I/O selects, but I only use a single page for I/O which allows each select to be 32 bytes wide. You can also take a look at Daryl's SBC-2 board/schematic linked here:

http://sbc.rictor.org/sch2.html

Using a single page (256 bytes) will save you more memory and still give you ample addressing space for I/O devices. As a side note, I'm using 74HC logic for my board (74HC00, 74HC30, 74HC138) and have been running at 10MHz for almost two years without any issue.

Thank you!

Nope no special reason for using 2kb of adressing, I am completely new to this so I figured I would not paint myself into a corner. I am planning to connect the 6502 to my pc to be able to get input and output. After that I hope to be able to add a keyboard and further down the line probably a SwinSID and some kind of storage, so far I have a 6551 and a 6522. Will def. look into changing my memory map, thanks for the input

Btw I am using 74HCT and it looks like at the most I will be able to use a 2MHz oscillator.

/jan

[Briggs]

GARTHWILSON wrote:

64KB of memory space is absolutely huge for a beginner to fill; so I'd say you're not in any danger of running short. Fine-grained address-decoding schemes will however usually require greater logic delays, reducing your maximum operating speed. It will also take more board space (unless you use programmable logic). To keep the logic ultra simple (and to run considerably faster than the parts are rated for), I left 16KB for I/O on my workbench computer. I've been using it regularly for 20+ years, and the only thing I've ever needed more memory for is data arrays, never code. Daryl does offer a pre-programmed programmable logic IC for fine-grained address decoding though, at http://sbc.rictor.org/decoder.html .

I figured that I would only run at 1MHz or maybe 2MHz so then I can use more adress-decoding logic and avoid any holes in the memory map (dont really know why other than that it feels wrong to not be able to use as much RAM as possible). However it might be that I end up scrapping it and going for a more leaner scheme since I had not about that more logic means more breadboard space.

/jan

[floobydust]

Hello Jan,

Clock speed limitation is likely to be more dependent on your 65xx parts. As you already have a 6551/6522, standard parts are rated for 1 or 2 MHz, albeit Rockwell did some CMOS versions that were rated at 4MHz. For anything new, I would get the current WDC W65C02 processor. The pinout is slightly different but well worth the slight change in board layout due to the lower current requirements, enhanced instruction set and stronger output drive. WDC also have the W65C22 and W65C51... all in CMOS.

Seems your logic already consists of 3 chips, so no issue for growing board space or complexity to get some of the memory addressing space back. Also note that you need to qualify read/write for the memory with the PH2 clock of the CPU with the R/W line. Daryl's SBC-2 is a classic example of decoding and memory access with 3 chips.

[Briggs]

Hi,

I should have written that I have the w65c02 processor and also the w65c22 and the w65c51

Yep I guess the hardest part is to accept that the project will need a couple of iterations before it is "perfect" and since the memorymap is something I can fiddle with on the bus to and from work it easily becomes the center of attention.

At the moment I am focussing on just getting the 65c02 to work or rather to see that it works. Next up is to copy http://lateblt.tripod.com/6502prj1.htm this setup and see how it works.

I am more or less a complete beginner in the field even though i have been working as software developer for 15 years. So I learn a lot but it also takes a lot of time and I do sooo many mistakes, for the moment I am glad that nothing have broken yet! Or uhm it might just be that I don't realise it

/jan

[floobydust]

Ah, good to know.... however, if your W65C51 is the most recent part, there is a bug with the chip. The Xmit register bit in the status register is stuck on, so you can't use it to determine when the Xmit register is empty. You'll need to use a delay routine based on the baud rate between sending characters. A search of the forum will find the details on this and show some sample code for a delay routine as well. WDC are aware of the problem, unfortunately there is no planned fix at the moment. WDC did update the datasheet with this information however.

[Briggs]

floobydust wrote:

Ah, good to know.... however, if your W65C51 is the most recent part, there is a bug with the chip. The Xmit register bit in the status register is stuck on, so you can't use it to determine when the Xmit register is empty. You'll need to use a delay routine based on the baud rate between sending characters. A search of the forum will find the details on this and show some sample code for a delay routine as well. WDC are aware of the problem, unfortunately there is no planned fix at the moment. WDC did update the datasheet with this information however.

Ouch! Thank you very much

[BigDumbDinosaur]

Briggs wrote:

Btw I am using 74HCT and it looks like at the most I will be able to use a 2MHz oscillator.

Actually, what you want is 74HC or 74AC logic, not 74HCT. 74HCT logic is only necessary if you have NMOS devices driving CMOS devices, which you say you don't have. In the otherwise same device, 74xCT will be slower than 74xC.

Assuming proper construction methods and a reasonable design, 74HC logic will be stable to at least 8 MHz (although you may be able to go faster in some cases) and 74AC logic will be stable at anything up to 14-15 MHz. Propagation delays through the glue logic will set the maximum speed at which your circuit will reliably run.

BTW, welcome to our 6502 world.

[Briggs]

BigDumbDinosaur wrote:

Actually, what you want is 74HC or 74AC logic, not 74HCT. 74HCT logic is only necessary if you have NMOS devices driving CMOS devices, which you say you don't have. In the otherwise same device, 74xCT will be slower than 74xC.

Assuming proper construction methods and a reasonable design, 74HC logic will be stable to at least 8 MHz (although you may be able to go faster in some cases) and 74AC logic will be stable at anything up to 14-15 MHz. Propagation delays through the glue logic will set the maximum speed at which your circuit will reliably run.

Oh, thank you! Ok, the next iteration will be a bit different from the first it seems as long as I do not incorporate any NMOS devices at least. There is really alot to learn which is part of why I like it.

BigDumbDinosaur wrote:

BTW, welcome to our 6502 world.

Than you

/jan

[Briggs]

floobydust wrote:

First, welcome to the the forum!

Seems your basic memory map is fine, but you are allocating 2KB of addressing to your I/O devices. Any particular reason for something this large? What I/O devices are you planning on using once you get the board up and running? My small CPU board has 8-I/O selects, but I only use a single page for I/O which allows each select to be 32 bytes wide. You can also take a look at Daryl's SBC-2 board/schematic linked here:

http://sbc.rictor.org/sch2.html

Using a single page (256 bytes) will save you more memory and still give you ample addressing space for I/O devices. As a side note, I'm using 74HC logic for my board (74HC00, 74HC30, 74HC138) and have been running at 10MHz for almost two years without any issue.

Doh, I did read about his encoding awhile ago but certain things don't really take hold until you get shown them again. My example would have used an 8 inpu NAND and would only have used 5 of those inputs, figured I would tie the other ones high. Looked at it again and it magically comes together with the whole 8input NAND being used and me only using 256 bytes for I/O which I agree is a much cleaner solution Thanks again!

[GARTHWILSON]

Briggs wrote:

GARTHWILSON wrote:

64KB of memory space is absolutely huge for a beginner to fill; so I'd say you're not in any danger of running short. Fine-grained address-decoding schemes will however usually require greater logic delays, reducing your maximum operating speed. It will also take more board space (unless you use programmable logic). To keep the logic ultra simple (and to run considerably faster than the parts are rated for), I left 16KB for I/O on my workbench computer. I've been using it regularly for 20+ years, and the only thing I've ever needed more memory for is data arrays, never code. Daryl does offer a pre-programmed programmable logic IC for fine-grained address decoding though, at http://sbc.rictor.org/decoder.html .

I figured that I would only run at 1MHz or maybe 2MHz so then I can use more adress-decoding logic and avoid any holes in the memory map (dont really know why other than that it feels wrong to not be able to use as much RAM as possible). However it might be that I end up scrapping it and going for a more leaner scheme since I had not about that more logic means more breadboard space.

1MHz is plenty fast for some applications. In fact, my first commercial computer design (approximately 1986) ran a 65c02 at 170kHz most of the time (to save battery power), and kicked the clock speed up to 1MHz only for brief times for chains of floating-point calculations. The whole computer only took 2mA, including the LCD. (BTW, later I learned that the job could have been done just as well with scaled-integer math (even without the tables), and would have made for a lot less overhead.)

However, if more execution speed is needed, keep in mind that there's a speed/memory trade-off, where slowing it down for more-fine-grained address decoding may cause you to need to straightline more code to get the needed speed, thus eating up the extra memory you thought you were getting.

[Briggs]

GARTHWILSON wrote:

1MHz is plenty fast for some applications. In fact, my first commercial computer design (approximately 1986) ran a 65c02 at 170kHz most of the time (to save battery power), and kicked the clock speed up to 1MHz only for brief times for chains of floating-point calculations. The whole computer only took 2mA, including the LCD. (BTW, later I learned that the job could have been done just as well with scaled-integer math (even without the tables), and would have made for a lot less overhead.)

However, if more execution speed is needed, keep in mind that there's a speed/memory trade-off, where slowing it down for more-fine-grained address decoding may cause you to need to straightline more code to get the needed speed, thus eating up the extra memory you thought you were getting.

You are talking about when instead of saving memory by doing for example a loop you write the whole content of the loop so to increase speed, right? Did not think about that either! This is really like opening a can of worms

Had I known everything I know now when I started the project I am not sure I would have started it. Sometimes ignorance is bliss, but only sometimes, I like the learning part.

[GARTHWILSON]

Briggs wrote:

You are talking about when instead of saving memory by doing for example a loop you write the whole content of the loop so to increase speed, right? Did not think about that either! This is really like opening a can of worms

An example in the work project above was that when speed didn't matter, I could move five-byte floating-point virtual registers using not only the loop, but the loop was in a subroutine, in only in place in the code, making it all the more memory-efficient; but then it also presented the additional delays incurred by the subroutine call and return. But when I needed maximum speed, not only did I kick the clock speed up, but I also avoided the subroutine call and the looping, and straightlined the code. I think the whole program took something like 24KB, and I had 32KB, so I wasn't in danger of running out; but all the fast moves did take up a lot of memory when I couldn't use the slow looping subroutine method.