VIA shift register

[LGB]

Hi,

I'm writing a software based emulator of a 65C22 VIA, also because to get it to know better. Shift register (SR) is especially confusing for me, since I've never needed it. I try to follow WDC's documentation, however there is something I can't understand. The documentation states that reading/writing the shift register starts the shifting (now let's talk about the internal clock mode for example the one based on PHI2). But then, what happens if want to shift-in a byte? By reading the result (shift is ready by checking IFR), it means to access the SR register which starts another shift round, I don't want! It's can be with the actual hardware too, as you may skip a byte my mistake because reading the result itself shifts-in another byte you don't want then, for example. The next "real" shift-in starts after a while forgetting about the previous. Am I really right that it works this way? Then you should disable shifting (eg reset bits 4 - 2 in ACR) before reading the result from SR, and it eliminates the problem of unwanted shift. Or is there any other solution? Thanks!

[GARTHWILSON]

That sounds like more or less it. Also, the very first read will be discarded, because you're reading to start the first shift in that case. So changing the mode should work. There is the bug about shifting in under control of an external shift clock, but if you're not going to shift in anyway, I guess it won't matter. Just put a passive pull-up on CB1 to hold it high while neither end is driving it. I can't take the time to try it right now, but I've used the SR a lot so I hope this little bit saves you some time.

[fachat]

I normally use the Rockwell data sheet I have, it has a number of timing diagrams for the shift register as well.
May be also found here: http://www.6502.org/documents/datasheets/rockwell/

André