6502.org

Mouser sent me the wrong type of VIA 65c22, the S version instead of the N version. I ordered an N, the invoice says N, the little label on the anti-static bag says N, the chip has an S printed on it. Argh.

So after my initial attack of huffy-puffy righteous annoyance, I re-read the data sheet for the 65c22 (which was not really helpful) and then Garth's texts on the matter (http://6502.org/tutorials/interrupts.html, http://wilsonminesco.com/6502primer/IRQconx.html, and viewtopic.php?f=1&t=1953&p=16482&hilit=65C22S#p16482, which were). Now I'm wondering if this is not a Good Thing. If I understand the differences correctly, the S totem-pole interrupts are slightly faster, but need a bit more glue logic. The other interrupt source in the computer is a 2692A DUART, which has an open-drain output that needs to be pulled up by a resistor. Adapting Garth's drawing (of the circuit, not the cartoons, never the cartoons), I'm thinking the logic would look something like this:
As for the actual implementation, here is where I would be grateful for guidance. Since I'm going to use a bunch of 74HC132 NAND gates in the design anyway (which come with those nice Schmitt triggers), I was thinking of NANDing instead of ANDing, and then feeding that signal back on itself in a second NAND gate to invert it the way we need it. Something like this:
However, that means we go through the chip twice. Data sheet tells me that this would cost a 2 x 11 ns delay. I have no feeling at all if this is a lot. It doesn't really seem that way, given I'm aiming for a 1 MHz clock, with anything above that "nice to have". Still, would it be worth including a "real" AND chip and saving those 11 ns? More generally, how long of a delay in the glue logic should make me worry?

Thanks.

Outdated cartoons notwithstanding , the few ns delay on interrupts will be pretty insignificant. It definitely won't keep anything from working like excessive delays in address decoding would. 11ns difference with a 1MHz clock will only mean that one time out of about 350 (on average), the servicing of the interrupt will get delayed by one instruction. Hardly a big deal.

That is a cycle time of 1000ns. So the worst case extra delay is 7000ns (just missed before a max 7 cycle instruction like an ASL abs,x) + 2*11ns (propagation delays of the NANDs).

Don't worry about the extra 22ns when you are OK with a 1Mhz clock.

Actually, if you have to use thru-hole ones, carbon-composition resitors are often better at high frequencies. The few times we used resistors in VHF power amplifiers when I worked in applications engineering at a VHF/UHF power transitor manufacturer in the mid-1980's, they were intentionally carbon composition. The reason is that the carbon film and metal film ones have a spiral cut in them to adjust the value in manufacture and make them very exact, and that spiral adds inductance. The absense of this in the carbon-composition ones is why their tolerance was so bad while the film ones are usually far more accurate than their gold (or other) tolerance band indicates. In this case though, a little inductance might even be a good thing, increasing the pull-up speed.

Ah. So we'd be looking at something like this?
Hard to argue with the simplicity and size. Since this SBC is only going to have a 2692A and one VIA 65c22, that will be just fine. Thanks!

The clock speed -- I'll try to follow the recommendations of the high-speed primer (viewtopic.php?t=2029), but start out with 1 MHz as a goal. Of course I'm hoping it will work at faster speeds, but at this point, getting it to work at all is the primary goal .

As for the discussion about F vs HC and metal vs carbon resistors -- is there some entry in the forum I might have missed about the other logic families as related to the 6502? I've read the Primer entry (http://wilsonminesco.com/6502primer/LogicFamilies.html), but now I've seen HCT, ACH, and F mentioned. I can look the general information up on them (http://www.eng.yale.edu/ee-labs/morse/compo/logic.html for example, or http://www.beam-wiki.org/wiki/7400_Families), but that doesn't tell me what to use for a 6502. For example, if F is so much faster, why don't I just use it for everything? (Judging from my catalogues, I'm guessing the F family doesn't offer all the chips available as HC.)

I know there are a bunch of real EEs here who can rattle this stuff down dead drunk at four in the morning, but for those of us who are coming from a software side and secretly always thought that logic chips are just another form of lego, seriously, how hard can it be, something as simple as "use metal resistors for wire wrap" or "use HC unless you want to be very, very fast, then use F" would be an enormous help and hopefully cut down on noob questions like mine (cough). Sorry if this is already on the forum and I missed it.

On that note, I should like to take this moment to say a big thank you again for the enormous amount of information and great help provided here. I don't think I've learned as much this quickly since college, if then. It's very much appreciated.

(EDIT: Corrected drawing, thanks to Arlet. This was actually a very instructional mistake, because it made me realize I've been thinking in terms of how "the signal" is flowing (from the 65c22 to the 65c02) instead of the actual electricity. Still annoying, of course.)

I think your diode needs to be reversed.

Yes, you're totally right, and even after BDD said how to do it correctly. Thanks, though I won't have a chance to correct the drawing until this evening. Comes from thinking of the way "the signal" is going and not where high and low is.

The "F" series is old (F)aster Bipolar and not CMOS, it eats up a "lot" of power. Try to stay with HC/HCT or AC/ACT (faster) since it's newer tech. and takes much less power.

Thanks for all of that. In summary, if I'm understanding this correctly, for the 65c02 HC has the best selection of chips, but AC is faster and should be used whenever possible for PDIP needs. Unless, that is, we need to connect lots of chips to one output and are worried about fan-out. In that case, we use ABT. F is super fast but uses lots of power, so it should be used only when we really, really need max speed (as with above interrupt example). LS is ancient and lots of the newer stuff doesn't come as PDIP.

There is one LS chip I've come across that sounds like lots of fun to play around with and doesn't seem to have been ported to the more modern technology: The 74LS181 ALU (http://en.wikipedia.org/wiki/74181). Amazing to think something like that was in the PDP-11.
Wire wrap. This is partially because of Garth's persuasive arguments (http://wilsonminesco.com/6502primer/WireWrap.html), partially because of the "all made by hand" idea (which is why I'm not using CPLD or other programmable logic chips, which I definitely will look into for any second computer), partially because, truth be told, I think it just looks cooler. And I don't need the added learning curve of the circuit design programs top of everything else at the moment.

Oh, and the CPU will be a WDC65c02 (already got it). Now that I've started using the BRA etc instructions in the emulator, I can't really imagine going back. That's why I'm staying away from 65816 emulators, by the way. I'm too afraid I'd get hooked on 16 bit instructions .

Thanks again!