IRQ with the 65c22S instead of the 65c22N (with 2692A)

[scotws]

Mouser sent me the wrong type of VIA 65c22, the S version instead of the N version. I ordered an N, the invoice says N, the little label on the anti-static bag says N, the chip has an S printed on it. Argh.

So after my initial attack of huffy-puffy righteous annoyance, I re-read the data sheet for the 65c22 (which was not really helpful) and then Garth's texts on the matter (http://6502.org/tutorials/interrupts.html, http://wilsonminesco.com/6502primer/IRQconx.html, and viewtopic.php?f=1&t=1953&p=16482&hilit=65C22S#p16482, which were). Now I'm wondering if this is not a Good Thing. If I understand the differences correctly, the S totem-pole interrupts are slightly faster, but need a bit more glue logic. The other interrupt source in the computer is a 2692A DUART, which has an open-drain output that needs to be pulled up by a resistor. Adapting Garth's drawing (of the circuit, not the cartoons, never the cartoons), I'm thinking the logic would look something like this:

As for the actual implementation, here is where I would be grateful for guidance. Since I'm going to use a bunch of 74HC132 NAND gates in the design anyway (which come with those nice Schmitt triggers), I was thinking of NANDing instead of ANDing, and then feeding that signal back on itself in a second NAND gate to invert it the way we need it. Something like this:

However, that means we go through the chip twice. Data sheet tells me that this would cost a 2 x 11 ns delay. I have no feeling at all if this is a lot. It doesn't really seem that way, given I'm aiming for a 1 MHz clock, with anything above that "nice to have". Still, would it be worth including a "real" AND chip and saving those 11 ns? More generally, how long of a delay in the glue logic should make me worry?

Thanks.

[GARTHWILSON]

Outdated cartoons notwithstanding , the few ns delay on interrupts will be pretty insignificant. It definitely won't keep anything from working like excessive delays in address decoding would. 11ns difference with a 1MHz clock will only mean that one time out of about 350 (on average), the servicing of the interrupt will get delayed by one instruction. Hardly a big deal.

[BigDumbDinosaur]

scotws wrote:

Mouser sent me the wrong type of VIA 65c22, the S version instead of the N version. I ordered an N, the invoice says N, the little label on the anti-static bag says N, the chip has an S printed on it. Argh.

Guess someone at Mouser doesn't know the alphabet. Seriously, this sort of goof-up is rare with them, but...

Quote:

So after my initial attack of huffy-puffy righteous annoyance, I re-read the data sheet for the 65c22...Now I'm wondering if this is not a Good Thing.

The 65C22N is intended for replacing the old NMOS 6522 in units that used the NMOS 6502. As such, it has the open-drain IRQ output, along with current limiting resistors on the signal outputs. You're ultimately better off with the 65C22S.

Quote:

If I understand the differences correctly, the S totem-pole interrupts are slightly faster, but need a bit more glue logic.

The internal logic in the 65C22S isn't any faster than in the 65C22N. Where the totem-pole output helps is in greatly reducing the time it takes for /IRQ to go high once all interrupt sources have been cleared. If the rise time is excessive you may run into trouble with spurious (aka phantom) interrupts that will drive you to drink.

Quote:

The other interrupt source in the computer is a 2692A DUART, which has an open-drain output that needs to be pulled up by a resistor. Adapting Garth's drawing (of the circuit, not the cartoons, never the cartoons), I'm thinking the logic would look something like this...

As for the actual implementation, here is where I would be grateful for guidance. Since I'm going to use a bunch of 74HC132 NAND gates in the design anyway (which come with those nice Schmitt triggers), I was thinking of NANDing instead of ANDing, and then feeding that signal back on itself in a second NAND gate to invert it the way we need it...

If there's any one place where you don't want to introduce unnecessary delay it's in the IRQ circuit. I absolutely would not do what you describe in your second illustration. Aside from the added delay between the generation of an IRQ and receipt of it at the microprocessor, there's the Rube Goldberg factor to consider.

You have two approaches to take:

1. You can use Garth's circuit, using a 74F08 (2-input quad AND gate) or for a bit more expansion capability (e.g., more 65C22's in the system, a 74F21 (4-input dual AND gate) (see attached datasheets below). I recommend the 74F logic because its internal propagation time on a low-to-high transition is no more than 5.3 ns at standard conditions. The MPU wants to see the sharpest possible transition at its IRQ input, and this is the way to achieve it. An alternative to the 74F08 is the 74AC08, which is a hair slower at 6.3 ns. The 74F08 has better fanout, but this isn't an issue if you place the gate close to the MPU to keep the interconnection as short and direct as possible.
   
   The main advantage of doing it with a gate is that you can connect multiple 65C22s to the circuit. As the output of the gate actively drives the MPU's IRQ input in both directions, a spurious IRQ from one of the 65C22s is highly unlikely. You can still run into trouble with spurious IRQs in the 2692's IRQ circuit if you make that connection to the gate excessively long. Incidentally, I'd reduce your pullup resistor to 2.2K and use a 1/8 watt metal film (best) or carbon film (good) type to reduce reactive effects. Definitely avoid carbon comp resistors in any computer circuit that is expected to run faster than a five dollar pocket calculator.
2. You can dispense with the AND gate and set up a standard wired-OR IRQ circuit, the same as what you would use if the 65C22S weren't in the circuit. To attached the 65C22's IRQ output to the wired-OR circuit, you'd connect the anode of a Schottky diode to the wired-OR IRQ circuit and connect the diode's cathode to the 65C22's IRQ output. Connect the 2692A's IRQ output, as well as a pullup resistor, to your wired-OR circuit. When the 65C22 drives its IRQ output low, the diode will be forward biased and will pull the wired-OR IRQ circuit low. When the 65C22 IRQ output goes high, the diode will be reversed biased and the pullup resistor will return the wired-OR IRQ circuit to the high state. If the 2692 interrupts, it will pull the wired-OR IRQ circuit low, but since the diode will continue to be reversed bias, the 2692 will not affect the 65C22 and the circuit will work as expected.

If you don't plan to attach more than one 65C22 I'd go with the diode circuit. It's simpler and doesn't require anywhere near the board real estate of the AND gate. Regardless of which circuit you decide to use, be sure to keep the IRQ connections as short and direct as you can make them. A little over-design in this area is not a bad idea.

74f08_and_quad.pdf

(80.12 KiB) Downloaded 90 times

74f21_and_4input.pdf

(227.65 KiB) Downloaded 85 times

diode_schottky_npx_bat85.pdf

(126.05 KiB) Downloaded 115 times

[BigDumbDinosaur]

By the way, at what clock speed do you intend to run your system? Just curious.

[Klaus2m5]

scotws wrote:

...I'm aiming for a 1 MHz clock, with anything above that "nice to have"...

That is a cycle time of 1000ns. So the worst case extra delay is 7000ns (just missed before a max 7 cycle instruction like an ASL abs,x) + 2*11ns (propagation delays of the NANDs).

Don't worry about the extra 22ns when you are OK with a 1Mhz clock.

[BigDumbDinosaur]

Klaus2m5 wrote:

scotws wrote:

...I'm aiming for a 1 MHz clock, with anything above that "nice to have"...

That is a cycle time of 1000ns. So the worst case extra delay is 7000ns (just missed before a max 7 cycle instruction like an ASL abs,x) + 2*11ns (propagation delays of the NANDs).

Don't worry about the extra 22ns when you are OK with a 1Mhz clock.

Hmmm...I guess I didn't see the comment about a 1 MHz clock. I'm sure that when Scot gets the circuit working he'll want to run it faster.

That said, your logic (no pun intended) is a bit askew. The timing reference is electronic, not logical, in that too many gates in the IRQ circuit results in too much lag between when a device interrupts and when the MPU finds out about it.

[GARTHWILSON]

Quote:

I'd reduce your pullup resistor to 2.2K and use a 1/8 watt metal film (best) or carbon film (good) type to reduce reactive effects. Definitely avoid carbon comp resistors in any computer circuit that is expected to run faster than a five dollar pocket calculator.

Actually, if you have to use thru-hole ones, carbon-composition resitors are often better at high frequencies. The few times we used resistors in VHF power amplifiers when I worked in applications engineering at a VHF/UHF power transitor manufacturer in the mid-1980's, they were intentionally carbon composition. The reason is that the carbon film and metal film ones have a spiral cut in them to adjust the value in manufacture and make them very exact, and that spiral adds inductance. The absense of this in the carbon-composition ones is why their tolerance was so bad while the film ones are usually far more accurate than their gold (or other) tolerance band indicates. In this case though, a little inductance might even be a good thing, increasing the pull-up speed.

[BigDumbDinosaur]

GARTHWILSON wrote:

Actually, if you have to use thru-hole ones, carbon-composition resitors are often better at high frequencies. The few times we used resistors in VHF power amplifiers when I worked in applications engineering at a VHF/UHF power transitor manufacturer in the mid-1980's, they were intentionally carbon composition. The reason is that the carbon film and metal film ones have a spiral cut in them to adjust the value in manufacture and make them very exact, and that spiral adds inductance. The absense of this in the carbon-composition ones is why their tolerance was so bad while the film ones are usually far more accurate than their gold (or other) tolerance band indicates. In this case though, a little inductance might even be a good thing, increasing the pull-up speed.

The carbon comp resistors being made today are generally a poorer quality than what we used 25-30 years ago. I used thin film resistor SIPs for pullups in POC V1. Aside from having better AC characteristics, a lot less board real estate gets used. If I were using discretes, thought, I'd use metal or carbon film, not carbon comp. The current crop of carbon comps aren't even good in audio circuits, as far as I'm concerned. They are especially noisy in tube audio.

[scotws]

BigDumbDinosaur wrote:

Connect the 2692A's IRQ output, as well as a pullup resistor, to your wired-OR circuit.

Ah. So we'd be looking at something like this?

Hard to argue with the simplicity and size. Since this SBC is only going to have a 2692A and one VIA 65c22, that will be just fine. Thanks!

The clock speed -- I'll try to follow the recommendations of the high-speed primer (viewtopic.php?t=2029), but start out with 1 MHz as a goal. Of course I'm hoping it will work at faster speeds, but at this point, getting it to work at all is the primary goal .

As for the discussion about F vs HC and metal vs carbon resistors -- is there some entry in the forum I might have missed about the other logic families as related to the 6502? I've read the Primer entry (http://wilsonminesco.com/6502primer/LogicFamilies.html), but now I've seen HCT, ACH, and F mentioned. I can look the general information up on them (http://www.eng.yale.edu/ee-labs/morse/compo/logic.html for example, or http://www.beam-wiki.org/wiki/7400_Families), but that doesn't tell me what to use for a 6502. For example, if F is so much faster, why don't I just use it for everything? (Judging from my catalogues, I'm guessing the F family doesn't offer all the chips available as HC.)

I know there are a bunch of real EEs here who can rattle this stuff down dead drunk at four in the morning, but for those of us who are coming from a software side and secretly always thought that logic chips are just another form of lego, seriously, how hard can it be, something as simple as "use metal resistors for wire wrap" or "use HC unless you want to be very, very fast, then use F" would be an enormous help and hopefully cut down on noob questions like mine (cough). Sorry if this is already on the forum and I missed it.

On that note, I should like to take this moment to say a big thank you again for the enormous amount of information and great help provided here. I don't think I've learned as much this quickly since college, if then. It's very much appreciated.

(EDIT: Corrected drawing, thanks to Arlet. This was actually a very instructional mistake, because it made me realize I've been thinking in terms of how "the signal" is flowing (from the 65c22 to the 65c02) instead of the actual electricity. Still annoying, of course.)

[Arlet]

I think your diode needs to be reversed.

[scotws]

Arlet wrote:

I think your diode needs to be reversed.

Yes, you're totally right, and even after BDD said how to do it correctly. Thanks, though I won't have a chance to correct the drawing until this evening. Comes from thinking of the way "the signal" is going and not where high and low is.

[clockpulse]

scotws wrote:

if F is so much faster, why don't I just use it for everything? (Judging from my catalogues, I'm guessing the F family doesn't offer all the chips available as HC.)

The "F" series is old (F)aster Bipolar and not CMOS, it eats up a "lot" of power. Try to stay with HC/HCT or AC/ACT (faster) since it's newer tech. and takes much less power.

[BigDumbDinosaur]

scotws wrote:

BigDumbDinosaur wrote:

The clock speed -- I'll try to follow the recommendations of the high-speed primer (viewtopic.php?t=2029), but start out with 1 MHz as a goal. Of course I'm hoping it will work at faster speeds, but at this point, getting it to work at all is the primary goal .

Which construction method do you plan to use? That will have some influence on the maximum Ø2 rate that can be reliably supported. A tight wire-wrap unit may be able to perform at speeds up to 8 MHz, assuming the logic is sufficiently fast. Point-to-point (soldered) will be slower and patch-board construction even slower. However, any reasonable design should be able to achieve 1 MHz.

Quote:

As for the discussion about F vs HC and metal vs carbon resistors -- is there some entry in the forum I might have missed about the other logic families as related to the 6502?

The discussion pops up here and there, but is not gathered into a single area, as far as I know.

Are you using a 6502 or a 65C02? If the former, you are working with an NMOS device that operates at standard TTL logic levels. Some caution with selecting logic families is necessary—note that the 65C22S and 2692 are CMOS devices. The W65C02S is the better MPU choice, due to a number of electrical characteristics (higher fanout being one of them—I'll get back to fanout in a minute) but also because it fixes implementation bugs present in the NMOS part. The W65C02S supports a wide range of Ø2 clock rates (up to 20 MHz in a well-designed circuit) and is recommended for all new eight bit designs. Beware of 65C02s sold by some vendors that are not WDC parts. Many are old Rockwell pulls rated for one or two megahertz.

Quote:

I've read the Primer entry (http://wilsonminesco.com/6502primer/LogicFamilies.html), but now I've seen HCT, ACH, and F mentioned. I can look the general information up on them (http://www.eng.yale.edu/ee-labs/morse/compo/logic.html for example, or http://www.beam-wiki.org/wiki/7400_Families), but that doesn't tell me what to use for a 6502.

The "high performance" logic families are: 74ABT, 74F, 74AC(T). 74F is a bipolar design that consumes more power than the 74ABT and 74AC designs but is commensurate in performance. I built my POC V1 units around 74AC logic in PDIP packages and was able to achieve stable operation at 12.5 MHz without the SCSI host adapter being installed. It would boot at 15 MHz, but I/O was flaky due to timing violations.

Fanout is a term that simplistically describes how many device inputs can be driven by a single output on a device. Low fanout is characteristic of 74LS, whereas 74ABT has the highest fanout of all presently-available devices. Fanout rating is a bit more complicated than just number inputs that can be driven, in that parasitic capacitance that is present to some extent in all designs counts as part of the load seen by the device's output. As well-designed PCB can have very small parasitic capacitance, which means that the fanout requirements are predominately due to the number and types of devices being driven. On the other hand, wire-wrap generally presents higher parasitic capacitance, which means the required fanout has to increase to maintain stable operation. Worst of all are patch-board units with wires running everywhere.

As for actual devices, CMOS inputs look mostly like capacitance during quiescent periods, with minute amounts of current being drawn (microamperes). CMOS input current draw is only significant during switching from one state to the other. Plain MOS inputs present some DC loading, as well as capacitance, which means fanout requirements using 74LS logic will be higher than when using one of the CMOS families. This characteristic, as well as the slower propagation rate and weak fanout, is one of the reasons to avoid 74LS logic.

As loading increases due to device count and parasitic capacitance, so must the drive of each device output that is so loaded. If the device's output is weak (74LS and 74HC), rise and fall times will be significant and circuit instability will be likely. If the device's output is strong (74AC/74F/74ABT) then rise and fall times will be short (extremely so with 74ABT) and stability is enhanced. However, real fast switching can sometimes cause ringing, which may bring back instability. Again, a properly designed PCB will not likely fall victim to ringing, whereas wire-wrap or point-to-point construction may.

Quote:

For example, if F is so much faster, why don't I just use it for everything? (Judging from my catalogues, I'm guessing the F family doesn't offer all the chips available as HC.)

You're correct, in that not all devices are available in all families. For most hobby design, I'd recommend using 74AC logic, in which most (probably all) of the devices you might need is available. 74F and 74ABT are mostly available in standard gates and buffer/driver/transceiver types, where the advantages of single nanosecond prop time and high fanout are best used. Many of these devices are available only in SOIC or similar packages, not PDIP. Also, see above about the potential for ringing with the real fast logic families.

Quote:

On that note, I should like to take this moment to say a big thank you again for the enormous amount of information and great help provided here. I don't think I've learned as much this quickly since college, if then. It's very much appreciated.

College? What's that?

[BigDumbDinosaur]

scotws wrote:

I can look the general information up on them (http://www.eng.yale.edu/ee-labs/morse/compo/logic.html for example...

I forgot to mention that the above article is about 15 years out of date.

[scotws]

Thanks for all of that. In summary, if I'm understanding this correctly, for the 65c02 HC has the best selection of chips, but AC is faster and should be used whenever possible for PDIP needs. Unless, that is, we need to connect lots of chips to one output and are worried about fan-out. In that case, we use ABT. F is super fast but uses lots of power, so it should be used only when we really, really need max speed (as with above interrupt example). LS is ancient and lots of the newer stuff doesn't come as PDIP.

There is one LS chip I've come across that sounds like lots of fun to play around with and doesn't seem to have been ported to the more modern technology: The 74LS181 ALU (http://en.wikipedia.org/wiki/74181). Amazing to think something like that was in the PDP-11.

BigDumbDinosaur wrote:

Which construction method do you plan to use?

Wire wrap. This is partially because of Garth's persuasive arguments (http://wilsonminesco.com/6502primer/WireWrap.html), partially because of the "all made by hand" idea (which is why I'm not using CPLD or other programmable logic chips, which I definitely will look into for any second computer), partially because, truth be told, I think it just looks cooler. And I don't need the added learning curve of the circuit design programs top of everything else at the moment.

Oh, and the CPU will be a WDC65c02 (already got it). Now that I've started using the BRA etc instructions in the emulator, I can't really imagine going back. That's why I'm staying away from 65816 emulators, by the way. I'm too afraid I'd get hooked on 16 bit instructions .

Thanks again!