Socgen project

[jt_eaton]

I would like to introduce you to a opensource project that I have been maintaining on opencores.org

It's name is socgen and it provides a set of tools and tool flows so that a designer can easily create
and verify a system-on-chip (soc) on any home pc. It uses ip-xact to hold all the design metadata and makes
it easy to build and run test suites and synthesis flows.

Currently it has tool flows for Icarus verilog, Verilator, Covered and Xilinx ISE. These are all Zero-Cost tools.

I had been making copies of other opencores projects and using them as sample designs but I recently added two cores
that this group is using. One is Arlets 6502 design and the other is MichaelM's M65C02.

I now have them in the socgen database and running testcode that I made for another 6502 project. My goal is to add
more simulations to improve coverage ( toggle is now about 80%) and add some other tests for the alu. If anyone has any
code sets that they would like to donate then I would gladly accept them. Hopefully I can build up a robust suite that
and perform a robust screening for any new cores.

I do have Michaels sim also running but it locks up about 100 instructions after reset.

I could use any code that crasm can assemble. Create a full 64K image and tell me how to detect that the code finishes and
where to find pass/fail and I can do the rest.


I would like to invite anyone interested to down load socgen and run the tool flows yourself. I could use any feedback on
how socgen works and what problems are lurking. I tested it on Ubuntu 12.10 and could use feedback on issues with other distros.

Attached is a getting started guide.

Thanks


John Eaton

z3qmtr45@gmail.com

[ElEctric_EyE]

Klaus2m5 has written a functional test for the 6502 and presented it in this thread.

The other PDF's in your doc's folder from your project on opencores.org are good reading.

I've not had a chance to test your project out yet, just thought I'd say welcome.

[jt_eaton]

ElEctric_EyE wrote:

Klaus2m5 has written a functional test for the 6502 and presented it in this thread.

The other PDF's in your doc's folder from your project on opencores.org are good reading.

I've not had a chance to test your project out yet, just thought I'd say welcome.

--------------------------------------------------------------------------------------------------------------------------------------------------------------

Thanks for the pointer. I now have Klaus's test running on Arlet's code. Took 2.8 secs of sim time and 2 hours of wall time but it passed.

I also tried it on M65Org16 in 16/8 mode and it has problems. The IR is hardcoded to 16 bits so when dw=8 then you compare to 8 floating lines and nothing works.

That may work in a fpga since floats are tied to 0 but not in icaraus.

The reset system is also a mess. It will work in a fpga but you could never put it in an Asic

John Eaton

[GARTHWILSON]

John, uncheck the "disable BBcode" box to get the tags to work right.

[ElEctric_EyE]

jt_eaton wrote:

...I also tried it on M65Org16 in 16/8 mode and it has problems. The IR is hardcoded to 16 bits so when dw=8 then you compare to 8 floating lines and nothing works...
John Eaton

What is M65Org16?

[jt_eaton]

ElEctric_EyE wrote:

jt_eaton wrote:

...I also tried it on M65Org16 in 16/8 mode and it has problems. The IR is hardcoded to 16 bits so when dw=8 then you compare to 8 floating lines and nothing works...
John Eaton

What is M65Org16?

That would be:

https://github.com/ElEctric-EyE/verilog-6502

[BigEd]

Hi John,
if you go upstream and pick up my https://github.com/BigEd/verilog-6502 do you get good results? I would hope you would!
Cheers
Ed

[jt_eaton]

BigEd wrote:

Hi John,
if you go upstream and pick up my https://github.com/BigEd/verilog-6502 do you get good results? I would hope you would!
Cheers
Ed

Doesn't even compile.

You have the port BCD listed twice when you define BCD_ENABLE.



/*
* ALU
*/

ALU #(.dw(dw)) _ALU(
.clk(clk),
.op(alu_op),
.right(alu_shift_right),
.AI(AI),
.BI(BI),
.CI(CI),
.BCD(adc_bcd & (state == FETCH)), <============================================
.CO(CO),
.OUT(ADD),
.V(AV),
.Z(AZ),
.N(AN),
`ifdef BCD_ENABLED
.BCD(adc_bcd), <=============================================
.HC(HC),
`endif
.RDY(RDY) );

[ElEctric_EyE]

BCD mode isn't supported on Ed's. I completely removed it on mine, even the opcodes and flags.

Is there a way to bypass BCD mode in your testing?

[jt_eaton]

ElEctric_EyE wrote:

BCD mode isn't supported on Ed's. I completely removed it on mine, even the opcodes and flags.

Is there a way to bypass BCD mode in your testing?

Its not the testing thats the problem. If you `define BCD_ENABLE then you have a port that is listed twice in the instantiation but if you don't `define then the BCD port doesn't exist but is still listed once in the instantiation. You need to remove the extra one outside the `ifdef BCD_ENABLE

Also icarus doesn't like your STACKPAGE set up


parameter
ZEROPAGE = 0, // {dw{1'b0}}, // all zero
STACKPAGE = 1; // {(dw-1){1'b0}, 1}; // one


Use:



parameter dw_m1= dw -1;

parameter
ZEROPAGE = {dw{1'b0}}, // all zero
STACKPAGE = {dw_m1{1'b0}, 1'b1}; // one

[jt_eaton]

And while I'm at it you have a register named "bit" in cpu.v. This is a system verilog keyword and verilator won't accept it. Arlet's code used both bit and logic but I see that you fixed logic already

[ElEctric_EyE]

Just so we're on the same page about the .b core, there is an updated version I put in 2 days ago that addresses some if not all of the things you have pointed out. BTW, thanks for pointing them out.

[BigEd]

Sorry about the BCD messup - I've been merging in a couple of Arlet's fixes without verifying the result, which explains the bug.

I've also tweaked the sources for Icarus, and to remove some warnings when compiling for synthesis - hopefully the code is now in better shape.

A correction to EEye's statement: BCD is supported in 8-bit (6502) mode, but is optional, and is not supported in 16-bit (65Org16) mode. This holds for my fork of Arlet's core, but as EEye says, in his fork of my fork BCD support is absent.

The three forks won't ever be reconciled, as they have different goals. I do try to get Arlet's fixes down into mine, and EEye similarly.

Cheers
Ed

[ElEctric_EyE]

jt_eaton wrote:

...Thanks for the pointer. I now have Klaus's test running on Arlet's code. Took 2.8 secs of sim time and 2 hours of wall time but it passed.

I also tried it on M65Org16 in 16/8 mode and it has problems. The IR is hardcoded to 16 bits so when dw=8 then you compare to 8 floating lines and nothing works.

That may work in a fpga since floats are tied to 0 but not in icaraus.

The reset system is also a mess. It will work in a fpga but you could never put it in an Asic

John Eaton

Icaraus is dedicated for ASIC development?

If so, if the 65Org16.b core runs on a Xilinx Spartan 6 FPGA at 100MHz, how fast could it run on an ASIC?

[Arlet]

No, Icarus is just a free verilog simulator. He's just saying that the reset system won't work in an ASIC.