What is the 65Org16?

Do a search on Google for 65Org16 Site: 6502.Org to catch up if you desire more detail.

Simply stated, as many times before, it is a 16-bit equivalent of the original NMOS 6502 8-bit core originally created by Arlet Ottens in Verilog, but modified into 16-bit data, 32-bit address by BigEd. i.e BigEd has modified Arlet's 8-bit 6502 core into a 16-bit data bus 4GB addressable CPU with all NMOS 6502 commands intact!

I would like to further modify BigEd's 65Org16 Core. More will be explained later, but I would like to attempt adding a WDC65C02 PHX opcode first. Arlet has already shown us how to here.

If you are interested how we got to this stage, I would recommend at least skimming through the 6502.org threads below, feel free to add links if you know I've missed any...

They show a beginning desire to mold a bigger, better, faster 6502 type CPU. One that can be designed into a very capable FPGA, maybe approaching 1/2 ASIC speed, using a Spartan 6 QFP style package Xilinx FPGA.

Chapter 1.
Chapter 2.
Chapter 3.

NOTICE: I reserve the right to heavily edit this page in the future, as I have had a long day of work! Thank You ... Thanks Admin!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

or other search engine. I use ixquick.com because they don't keep a record of what you search for like Google does. The way our loss of freedoms is going, pretty soon they'll be carting you off as "domestic terrorists" because you looked up "water balloons" for your child's birthday party. ixquick.com works the same way as Google, but without keeping records for the nosey feds to look into.

Garth, don't make me go there!
I am posting here to lose myself in digital electronics! I did receive my Digilent USB JTAG Cable today, but I am tiring...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I have been working the past few days getting refamiliarized with the testbench I have used for the POC:65O16.b. Slightly modified (I'll post schematic soon), it's using BRAMs in the Spartan 6 containing a 4K Zero page RAM ($00000000-$00000FFF), an 4K Stack RAM ($0001F000-$0001FFFF) and a 4K "ROM" ($FFFFF000-$FFFFFFFF). The bugs have been worked out [/url]of it thanks to Arlet's help with some RAM timing signals, and making the .coe converter that is needed to convert an 8/16-bit .bin file into a .coe file for the Block Memory Generator.

Speaking of .bin files, the assembler Bitwise has written for us already seems to be 65C02 compatible. Thanks Bitwise! Quickly coding for PHX, PLX and STZ produced the expected results in the .bin file.

Tomorrow I'd like to get into modifying the 65Org16.b core, using Arlet's core as the reference, and testing it with ISim...

Work also progresses on the V1.1 DevBoard.

EDIT: added "16-bit" link.
EDIT: added "testbench" link, corrected memory sizes

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I've done coding PHX, PHY, PLX and PLY. Line #'s are referenced to Arlet's NMOS core. Whether they work or not I am about to find out, but they did pass synthesis.

To define the PHX($00DA), PHY($005A), and PLX($00FA),PLY($007A) in the Mircocode state machine I added the following after line 893 :


To define the behavior of PHX I added the following after line 1016:

For PHY I added the following after line 1022:

I'm pretty sure the previous will work. I'm not so sure about the following because I could not find PLA(0110_1000) in the code. I did find the mask for it on line 979 which is why I proceded this way:

To define the behavior of PLX & PLY I added the following after line 981:


Now off to testing in ISim...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

For the pull instructions, you need to set 'dst_reg', and for the 'push' instructions, you'll need to set 'src_reg'.

In a PLX for instance, the X is the destination. So, during PLX decode you'll need to set 'dst_reg', and the actual write to register X will be done during the next DECODE cycle (of the next instruction) (line 545)

For 'push' instructions, the data is fetched from the register file at line 650/651, during PUSH0. The data then goes into the ALU, where it comes back out one cycle later, during the PUSH1 cycle. In the PUSH1 cycle, the ALU output goes to DO bus in line 431, where it is written to the stack.

I was following the behavior of PLA($68,0110_1000) on your code on line 979 where you have a mask for xxxx_10x0. Is this the only place for the PLA opcode behavior definition? or am I missing something? Thanks! I will come back to your previous post, just need this answered.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Yes, line 979, but also line 1004.

Ok, I can't say I'm learning yet. I thought doing PHX, PHY, PLX, and PLY would have been easier, but I am still digesting the flow of it. At the same time I had to make adjustments to my testbench to accomodate the 4Kx16 .bin file that Bitwise's assembler makes. I was using address decoding for 8Kx16, for my earlier experiments using a hex editor. I really need to look at the HDL equivalent of the address decoding and study it. So many wires in schematic entry is a pain, especially when working with 32-bit addresses!

I'm happy to say a simple program I've made below appears to be running in ISim.


I need to head out for abit, but when I return I can run a Sim and post it. Which signals should we be focusing on? I know we will want to look at PC[31:0], IR[15:0], statename [47:0], X[15:0] and Y[15:0].

I have posted my changes to my version of the core on Github.

If these opcodes work I have 2 more instructions I/(we?) would like to tackle next. TXY and TYX...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

and also A, S, AI, BI, ADD, DI, DO, src_reg, dst_reg. That should cover most of the data path between stack and registers.

I was able to fit the entire loop of the program I previously posted, into the pic. I thought the src_reg and dst_reg were 16 bits looking at the code, after all they are transferring data between the A,X,Y, and Stack registers. I wish I could tell if it was working.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

They are 2 bit wide, and only contain the index of the register. See lines 75-82. So, whenever src_reg is equal to 2, that means that X is the source.

By the way, your code isn't working. The PHX instruction should cause a state = PUSH0, but it's going to REG instead.

This is because the $00da opcode is covered by line 893:



You'll need to change that pattern so it doesn't cover the new opcode(s)

I know this was your warning at the outset, I thought I had it covered. I need a few more days to re-check this out.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I'm at work so I'm on and off looking at your code....



I'm thinking for line 893: will work, since the extra opcodes shown below bits 5 & 7 are both 1.
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No, I can see that's not going to work either. Still thinking...

I think defining just about each one will have to be done like this:



Also, I'm going to have to worry about line 979 too aren't I?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502