6502.org

I got my Arty (plus a small TFT touch screen with SD card reader which hadn't been released yet) at the Hackaday SuperConference in November and it came with a voucher too, but I didn't need it. I was told the voucher was for an earlier version for which Artix FPGA support wasn't free. The current free version of Vivado supports the Arty and you can install it on as many computers as you want.

=== Jac

Thanks - that's good to know. I notice (with a little confusion) that ISE gets a mention in the reference materials. Possibly ISE proper can target this device but the free version can't. Or it can now, like the case with Vivado...

Both Altera and Xilinx provide IP modules for DDR3 modules. Details are different depending on hardware but basically you load a library and put a declaration in your HDL code to wire it up, from then on you just give the declared module a clock and an address and it takes care of reading/writing the data.

Disclaimer: I haven't tried it myself but I've seen sample code to do it and it doesn't look too hard to do.

=== Jac

From what I can tell, the 16-bit wide DDR3L RAM on this board would give an effective access time something like 10nS - does that match your expectations, Jac, Arlet? (Maybe truly random access would even be 3x longer?)

I'm sorry, I don't know at this time (see disclaimer above).

Edit: you just quoted a 667MHz spec on the RAM. That would imply an access time of 1.5 ns.

=== Jac

Fair enough!

I think it would be a terrible waste to do random access on a device like that. The FPGA is big enough for some caches.

Edit: can't say if your numbers are correct. I've never used DDR... never needed such performance in any project.

That's a good point, it does have heaps of block RAM - 200kBytes, plus 12.5% bonus bits.

Hi. Slightly OT. Yes, they are that amazing fast. Using a standard memory controller however there is about a 20+ cycle latency. So for random accesses the time is closer to 45 or 50 ns. There are some DDR ram controllers on Opencores.org. I’ve used the one supplied by the vendor (Xilinx) with the ddr2 ram operating at 600MHz. A lot of the cores return the entire burst of data in a single lower speed clock cycle, so system timing is easier to achieve. With the mig core 128 bits are returned at once at ¼ the DDR ram clock rate. In my case 75MHz. (The ddr2 clock rate is twice as slow as ddr2 is accessed, because ddr2 access use both edges of the clock). Useful for loading a cache. It’s best to use a cache with DDR ram, not totally random access.
A multi-port memory controller may also be required on top of the DDR controller. DDR controllers typically only provide a single port to RAM. For anything but the simplest of systems, there’s likely to be multiple bus masters that want access to the ram.

I see Numata have some smaller cheaper boards: Mimas V2, with LX9 and 512Mbit of x16 DDR RAM, for $50.

• 8 LEDs, Six Push Buttons and 8 way DIP switch for user defined purposes
  VGA Connector
  Stereo Jack
  Micro SD Card Adapter
  Three Digit Seven Segment Displays
  32 IOs for user defined purposes
  Four 6×2 Expansion Connectors

Four would have been much nicer.

I've had my eye on this board for a while now, as a possible target for the Beeb/Electron/Atom/System FPGA projects.

The main thing holding me back is the RAM is DDR, and it's not clear what cycle time could be achieved for random accesses.

(It's also missing a PS/2 connector for a keyboard, but that could be easily added)

The DDR is 166MHz 512Mb LPDDR (MT46H32M16LF)

There are open source SDRAM controller that hide some of the complexity, e.g.:
http://hamsterworks.co.nz/mediawiki/ind ... Controller

Has anyone tried using the SDRAM on an FPGA board for a retro computing project? I'm interested to hear how you got on.

Dave

Three possibly useful answers in this thread:
viewtopic.php?p=40716#p40716
- Arlet has a controller
- Rob uses the vendor controller
- JMP got something working

My controller doesn't do DDR though, so I would go with the built in controller.

Since no one mentions Lattice here, I just want to mention that I have successfully compiled several 6502 cores on the MachXO3L which can be bought as a starter kit (with USB interface for programming) for around 25USD.

Cheap, but without VGA or external RAM (but you can solder that on to its available pins if you need them). SPI and DRAM interfaces are freely available (as IP modules) along with the full free version of Lattice Diamond (full Verilog & VHDL programming environment with a simulator).

The CPLD on the board has about 6900 LUTs and 26KByte of cache memory (without using LUTs for that). Its internal programmable clock can run up to 133MHz, but there are IP modules to increase that (if you need to!).