The attachment clock_generator_2phase_modified.gif is no longer available
Green on a black background kinda sucks. (Oh! -- about the
circuit, you mean!
)
Picky, picky!
- Two-Phase Clock Generator w/Stop
Don't forget the humble JK flipflop (below). I've drawn this using 'AC112, but with trivial changes the 'AC109 will also work. (With J and /K tied together the '109 can masquerade as a '74, which increases the potential utility of the other flipflop section in the package.) With this circuit it's better if your /STP signal becomes valid before the rise of Phi2 (but I assume that's already the case).
Yes, that would work as well. Once advantage the 'AC74 has over the 'AC112 is the former is in a smaller package.
The CPLD logic is such that it would make a decision on wait-stating when
GCLK goes high. At that point, the effective address has settled and I have the whole of the
GCLK high phase in which to assert
/STP and stop everything. Similarly, when the wait-state expires,
/STP would be de-asserted during
GCLK high, keeping Ø2 in phase with
GCLK. In both case, so my thinking goes, the change of state of
/STP will always slightly lag the rise of
GCLK due to the CPLD's pin-to-pin delay (7-10ns), which should eliminate any glitches.
In any case, my main question is if my idea is even feasible.
On another topic, I noticed the following portion of your schematic (below). Maybe eight of those nine jumpers can be omitted. Assuming the 'ACT541 is in a socket...
The 'ACT541 is in an SOIC20 package, hence the jumper block.
