Dual port ram

[KhanTyranitar]

banedon wrote:

KhanTyranitar wrote:

....So my next major hurdles are: to either buffer or slow down for SID and ROM access. If I use faster ROMs, I won't need to worry about them. I may go with some type of flash memory for the ROMs as well, I'm not sure yet, just considering the option. If I can get the ROM figured out, then that leaves me with the SID chips. I plan to set it up for dual SIDS. Since the SID uses $d400-d7ff (a whole K) then is there a way I can trigger the CPU to slow down to 1 MHz when any address in that range is accessed? Or am I thinking about this the wrong way?

Hiya

You can delay the CPU when needed using a simple but elegant JK flip-flop circuit which has been posted somewhere on these forums (I'll try and dig it out). If memory serves, the circuit uses 3 inputs: PHI2 (the main clock), the active low device enable pin (ROM select, VIC select, etc.) and (optionally) the CPU reset pin. The output is to the RDY on the CPU.

Here's a version of it, but please note that I did not design this (kudos lies elsewhere) and it's done from memory so I've hopefully remembered it correctly! :

CPU_DELAY.gif

BTW hello to everyone: Long time, no see!

That looks pretty good. I guess my PHI2 would be the 1MHz PHI2?

[banedon]

KhanTyranitar wrote:

banedon wrote:

KhanTyranitar wrote:

....So my next major hurdles are: to either buffer or slow down for SID and ROM access. If I use faster ROMs, I won't need to worry about them. I may go with some type of flash memory for the ROMs as well, I'm not sure yet, just considering the option. If I can get the ROM figured out, then that leaves me with the SID chips. I plan to set it up for dual SIDS. Since the SID uses $d400-d7ff (a whole K) then is there a way I can trigger the CPU to slow down to 1 MHz when any address in that range is accessed? Or am I thinking about this the wrong way?

Hiya

You can delay the CPU when needed using a simple but elegant JK flip-flop circuit which has been posted somewhere on these forums (I'll try and dig it out). If memory serves, the circuit uses 3 inputs: PHI2 (the main clock), the active low device enable pin (ROM select, VIC select, etc.) and (optionally) the CPU reset pin. The output is to the RDY on the CPU.

Here's a version of it, but please note that I did not design this (kudos lies elsewhere) and it's done from memory so I've hopefully remembered it correctly! :

CPU_DELAY.gif

BTW hello to everyone: Long time, no see!

That looks pretty good. I guess my PHI2 would be the 1MHz PHI2?

You can go higher as long as your glue logic and RAM, ROM, etc. can keep up. The faster you go though the more you'll need to do to slow the clock for the VIC. Personally, I'd keep to 1 or 2MHz because of that - as you suggest

[KhanTyranitar]

KhanTyranitar wrote:

Ok, here is the schematic I have so far. It probably has some newb mistakes. It is obviously not the entire board, just the interface to the DP RAM, and the LATCH trigger (which is another circuit as well).

In regards to this schematic, my biggest area of concern is whether my timing is right. Obviously if I cross those it wont work.

[BigDumbDinosaur]

KhanTyranitar wrote:

KhanTyranitar wrote:

Ok, here is the schematic I have so far. It probably has some newb mistakes. It is obviously not the entire board, just the interface to the DP RAM, and the LATCH trigger (which is another circuit as well).

CDX_65816_DP_RAM.jpg

In regards to this schematic, my biggest area of concern is whether my timing is right. Obviously if I cross those it wont work.

I'd be concerned as well about the 74LS04s you have in the design. Those should be 74AC04 or 74HC04.

[KhanTyranitar]

Ok, I'll look into that.

[BigDumbDinosaur]

KhanTyranitar wrote:

Ok, I'll look into that.

Generally speaking, you should not mix logic types. 74LS operates at TTL voltage levels and has relatively weak fanout. It's best not used in new designs.

[Dr Jefyll]

KhanTyranitar wrote:

In regards to this schematic, my biggest area of concern is whether my timing is right.

It's not clear why you've placed transceivers on the address buses of the RAM. As with any RAM, the address lines are inputs. They never output a signal, so installing a transceiver in this way has no useful function that I can see. (The 74FCT16245 is a "stretch," 16-bit version of the well-known 8-bit 74_245 transceiver. According to the state of the DIRection pins, it can either input from its A port and output to its B port, or vice versa. But, installed as shown, there'll never be a need for the transceiver on the left to input from its B port, or for the transceiver on the right to input from its A port.)

It's an ambitious project you've laid out for yourself, so it's only natural that you'll be doing some climbing up the various learning curves. (There isn't anyone who was never a newbie.) Be sure to pay special attention to how logical operations perceived by the programmer are supported by the physical implementation of the machine -- including fundamental items such as RAM's, multiplexers, and the buses of the microprocessor itself. Regarding the microprocessor, a good reference is the MOS Hardware Manual, found here.

[KhanTyranitar]

Dr Jefyll wrote:

KhanTyranitar wrote:

In regards to this schematic, my biggest area of concern is whether my timing is right.

It's not clear why you've placed transceivers on the address buses of the RAM. As with any RAM, the address lines are inputs. They never output a signal, so installing a transceiver in this way has no useful function that I can see. (The 74FCT16245 is a "stretch," 16-bit version of the well-known 8-bit 74_245 transceiver. According to the state of the DIRection pins, it can either input from its A port and output to its B port, or vice versa. But, installed as shown, there'll never be a need for the transceiver on the left to input from its B port, or for the transceiver on the right to input from its A port.)

It's an ambitious project you've laid out for yourself, so it's only natural that you'll be doing some climbing up the various learning curves. (There isn't anyone who was never a newbie.) Be sure to pay special attention to how logical operations perceived by the programmer are supported by the physical implementation of the machine -- including fundamental items such as RAM's, multiplexers, and the buses of the microprocessor itself. Regarding the microprocessor, a good reference is the MOS Hardware Manual, found here.

The answer why the transceivers are there is because as controlled by the logic, ehich I am still trying to sort out, RAM at times needs to be hidden from the CPU or other devices. As in a C64 if I have a ROM banked in and I attempt to read it, I don't want to read RAM at the same address. But if I write to that same address, it needs to write to the RAM hidden under the ROM. If I turn off the ROMs then the RAM becomes fully available.

In the case of IO devices, they occupy memory space too and can be written to and read from, so in their cases I need to be able to selectively hide RAM as well. If the IO chips (CIA, SID, VIC-II) are disabled, then the RAM can be fully accessed. On the left side of the RAM is the CPU and any devices that can operate at higher speeds. One the right side is the 1 MHz bus which consists of chips that can't be clocked at higher speeds. The SID and CIA chips are passive and never try to read memory. But the VIC-II chip actively reads 40 memory addresses every 8 scanlines, hence the dual port RAM, which grants the VIC-II chip the ability to do so without having to halt the CPU. The VIC-II chip can also access the Character ROM even when it is hidden from the CPU. The Character ROM located at the same address as IO, but when the IO devices are on, the CPU can't see it.

I know it's all complicated. I did not pick an easy project. That being said, there is probably an easier solution to using the transceivers. I'm still playing around. I'm not commited on much on the design at this point. I'm not ordering many parts till the schematic looks good.

In regards to your comments, I suppose I could just use the OE pins on each side of the chip and get rid of the transceivers. I guess I was overthinking it.

[KhanTyranitar]

Ok, toggling OE won't work. The tranceivers effectively isolate the address bus.

[Dr Jefyll]

I think you had the right idea when you mentioned getting rid of the transceivers. You could just run those address lines straight in.

As for the RAM, pretend for a moment it's not dual-port but just an ordinary 62256 (32K bytes) or similar. You should study the Truth Table for such a device if you haven't already. You'll see it's perfectly happy to IGNORE what's on the address and data buses. It needs to be specifically instructed to either "speak" (read) or "listen" (write) -- sorry for the corny analogy! On a shared bus (like people sharing a conversation) there should never be more than one device talking at a time, and maybe sometimes there's none. The number which listen is usually one, although it's possible that there be none (or, in some designs, occasionally more than one).

Edit: oops, I overlooked a large paragraph you added to the post before last. It's usually the address presented by the bus master which determines which device will respond. An address decoding circuit manages this, resulting in signals that control the Chip-Select and/or Write Enables and Output Enables of the devices on the bus. In your case matters have an extra wrinkle due to the write-through into RAM. There'll be addresses for which the decoder must also consider the state of the R/W line, not just the address. Something else it'll consider is the state of the signal that says when the ROM has been switched out, and that reads will be fielded by the RAM.

I suggest you work this out one "side" at a time. For starters, at least, just pretend the dual-port RAM is two separate chips.

[KhanTyranitar]

Ok, been trying to wrap my head around everything again. I guess I misread something, and the solution should be to just control with CE0. Now my next question, in my schematic I connected the CE pins to clock cycles. I'm guessing the CE1 pin still needs to connect to a clock? Or is timing controlled simply by the address and RW lines?

[Dr Jefyll]

With 65xx family chips the convention is for nothing to drive the data bus except when Phase2 is high. (The Phase2-low time isn't suitable for moving data because the address bus is in flux due to being updated.)

The Truth Table for a RAM says nothing will happen unless Chip-Select and Write Enable are simultaneously active, or Chip-Select and Output Enable are simultaneously active. So, to obey the convention, during the Phase2-low time your logic needs to either force Chip-Select false, or force Write Enable and Output Enable false. Let's go with the latter option. Let's assume Output Enable only gets asserted when Phase2 is high and the CPU R/W line is high, and the Write Enable only gets asserted when Phase2 is high and the CPU R/W line is low.

A basic decoder circuit would need very little else. Basically you'd only have to create the equivalent of a gate, one that inputs the pertinent address lines and determines whether the current address is a match. The gate's output drives the Chip-Select, and now you've accounted for all the necessary conditions. The RAM won't activate outside the appropriate address range, it won't read when it should be writing or vice versa, and it's guaranteed to do nothing during the Phase2-low time.

It's much the same with other devices although there may be more conditions to account for. An example of this is when you implement the write-through feature. You have an extra input to consider -- the signal that says when the ROM has been switched out, and that reads will be fielded by the RAM. You could work that signal into the logic that drives CS, or work it into the logic that drives OE. So there's no rocket science, although the work can be laborious. Hope this helps! Studying the schematics of other machines is probably a good idea.

[KhanTyranitar]

Dr Jefyll wrote:

With 65xx family chips the convention is for nothing to drive the data bus except when Phase2 is high. (The Phase2-low time isn't suitable for moving data because the address bus is in flux due to being updated.)

The Truth Table for a RAM says nothing will happen unless Chip-Select and Write Enable are simultaneously active, or Chip-Select and Output Enable are simultaneously active. So, to obey the convention, during the Phase2-low time your logic needs to either force Chip-Select false, or force Write Enable and Output Enable false. Let's go with the latter option. Let's assume Output Enable only gets asserted when Phase2 is high and the CPU R/W line is high, and the Write Enable only gets asserted when Phase2 is high and the CPU R/W line is low.

A basic decoder circuit would need very little else. Basically you'd only have to create the equivalent of a gate, one that inputs the pertinent address lines and determines whether the current address is a match. The gate's output drives the Chip-Select, and now you've accounted for all the necessary conditions. The RAM won't activate outside the appropriate address range, it won't read when it should be writing or vice versa, and it's guaranteed to do nothing during the Phase2-low time.

It's much the same with other devices although there may be more conditions to account for. An example of this is when you implement the write-through feature. You have an extra input to consider -- the signal that says when the ROM has been switched out, and that reads will be fielded by the RAM. You could work that signal into the logic that drives CS, or work it into the logic that drives OE. So there's no rocket science, although the work can be laborious. Hope this helps! Studying the schematics of other machines is probably a good idea.

I'll go back through again to figure it out. The RAM I've chosen has two CEs per bank. In order to enable the RAM then CE0 has to be Low while CE1 has to be High. If this happens, then CE is considered to be true.

So to me it sounds like I could set CE1 with the PH2 clock, and control whether the chip is active with the logic circuit via CE0.

According to the truth table for my chip, the only time OE matters is when reading from RAM, in which case it has to be low. But otherwise it can always be in a low state and it won't have any effect on writing to RAM whether it is low or high. So I guess could time OE to CE0 or to inverted PH2. Or would it be better to use an inverted RW signal?

I have found your comments to be quite helpful.

Now another question regarding the timing signals. In different diagrams and schematics, I'm seeing references to PH0, PH1, and PH2. Some call for a CLK1 and CLK2. I find it very confusing. Is PH0 and PH1 used interchangeably or are they different?

[Hobbit1972]

KhanTyranitar wrote:

Now another question regarding the timing signals. In different diagrams and schematics, I'm seeing references to PH0, PH1, and PH2. Some call for a CLK1 and CLK2. I find it very confusing. Is PH0 and PH1 used interchangeably or are they different?

Normally phi0 is the base clock that is fed

either into CPU or into external circuit

which then generates phi1 (=lagging a few ns behind phi0) and phi2 (=non-overlapping inverted phi1). Relevant for system timing is phi2 as in 65xx during phi2 will happen memory transfers.


If you can do something useful with phi0 depends on your circuit as it is slightly out of sync with phi2. phi1 might come handy if inverted phi2 is needed. In some systems you will find a delayed phi2' if needed.

[KhanTyranitar]

Hobbit1972 wrote:

KhanTyranitar wrote:

Now another question regarding the timing signals. In different diagrams and schematics, I'm seeing references to PH0, PH1, and PH2. Some call for a CLK1 and CLK2. I find it very confusing. Is PH0 and PH1 used interchangeably or are they different?

Normally phi0 is the base clock that is fed

either into CPU or into external circuit

which then generates phi1 (=lagging a few ns behind phi0) and phi2 (=non-overlapping inverted phi1). Relevant for system timing is phi2 as in 65xx during phi2 will happen memory transfers.


If you can do something useful with phi0 depends on your circuit as it is slightly out of sync with phi2. phi1 might come handy if inverted phi2 is needed. In some systems you will find a delayed phi2' if needed.

Ok, so PH0 is only for timing the CPU. My CPU (65816) does not have a PH1 or PH2 output which means I must generate those signals externally. What is the cleanest way to generate those signals? Flip-flop?