Dr Jefyll wrote:
KhanTyranitar wrote:
In regards to this schematic, my biggest area of concern is whether my timing is right.
It's not clear why you've placed transceivers on the address buses of the RAM. As with any RAM, the address lines are inputs. They never output a signal, so installing a transceiver in this way has no useful function that I can see. (The 74FCT16245 is a "stretch," 16-bit version of the well-known 8-bit 74_245 transceiver. According to the state of the DIRection pins, it can either input from its A port and output to its B port, or vice versa. But, installed as shown, there'll never be a need for the transceiver on the left to input from its B port, or for the transceiver on the right to input from its A port.)
It's an ambitious project you've laid out for yourself, so it's only natural that you'll be doing some climbing up the various learning curves. (There isn't anyone who was never a newbie.) Be sure to pay special attention to how logical operations perceived by the programmer are supported by the physical implementation of the machine -- including fundamental items such as RAM's, multiplexers, and the buses of the microprocessor itself. Regarding the microprocessor, a good reference is the MOS Hardware Manual, found
here.
The answer why the transceivers are there is because as controlled by the logic, ehich I am still trying to sort out, RAM at times needs to be hidden from the CPU or other devices. As in a C64 if I have a ROM banked in and I attempt to read it, I don't want to read RAM at the same address. But if I write to that same address, it needs to write to the RAM hidden under the ROM. If I turn off the ROMs then the RAM becomes fully available.
In the case of IO devices, they occupy memory space too and can be written to and read from, so in their cases I need to be able to selectively hide RAM as well. If the IO chips (CIA, SID, VIC-II) are disabled, then the RAM can be fully accessed. On the left side of the RAM is the CPU and any devices that can operate at higher speeds. One the right side is the 1 MHz bus which consists of chips that can't be clocked at higher speeds. The SID and CIA chips are passive and never try to read memory. But the VIC-II chip actively reads 40 memory addresses every 8 scanlines, hence the dual port RAM, which grants the VIC-II chip the ability to do so without having to halt the CPU. The VIC-II chip can also access the Character ROM even when it is hidden from the CPU. The Character ROM located at the same address as IO, but when the IO devices are on, the CPU can't see it.
I know it's all complicated. I did not pick an easy project. That being said, there is probably an easier solution to using the transceivers. I'm still playing around. I'm not commited on much on the design at this point. I'm not ordering many parts till the schematic looks good.
In regards to your comments, I suppose I could just use the OE pins on each side of the chip and get rid of the transceivers. I guess I was overthinking it.