[WORKING] Simple 6502 SBC from scratch (Deck65)

[pjdennis]

and3rson wrote:

Your suggestion of using one of those boards for clock actually gave me an idea to use Nano as a simulator for DIP-28 ROM! I think there *should* be enough pins (12 addr + 8 data + /CE & /RD interrupts) for the task. Also, I'm not sure if 16MHz will be enough for this, I'll see if I manage to write a code that will take less than 8 CPU cycles of Nano to read the data (and I have serious doubts about this). As a last resort, I can just underclock my W65C02S so that Nano has more time to assert the data line.

If you generate the CPU clock from the Arduino, then timing is not a problem since you can synchronize the memory simulation with the generated clock within the Arduino code. You won't break speed records but it's perfectly fine for experimentation - I've done this, but using an Arduino Mega (which has plenty of pins to cover the full 16-bit address space if needed.)

A small step further is to support in-circuit programming of an EEPROM using the Arduino, which if given control of the 65C02 BE bus enable line, can take the CPU off the bus during the programming operation. I have this working, but haven't used it much since I currently find it more convenient during code development to upload directly into RAM from a PC using a USB to "TTL" converter, with fixed loader software in EEPROM.

[BigDumbDinosaur]

and3rson wrote:

Michael wrote:

You could also use an Uno or a Nano as a temporary clock source...

Be careful with these “roll your own” clock solutions. WDC specifies that the rise/fall time of the clock input not be greater than 5ns, and in a five volt system, the signal amplitude must swing between near-ground (0.4 volts) and VCC × 0.7 (3.5 volts). Said requirements eliminates a number of logic families from clock-generation duties, as well as some MCUs, whose output rise/fall times are too slow.

Quote:

EDIT: Note to future self - "never put EPROMs in the middle of the board with too many jumpers around, you'll need to remove it pretty often..."

Using a ZIF socket will ease the pain. Your idea of using an MCU to emulate a ROM is inserting unnecessary complexity into a circuit that is completely untested. Should your unit be DOA, you’ll have two separate troubleshooting paths to investigate.

[and3rson]

Man, breadboards get nasty real fast. I think I'll stick to my trusty ol' soldering station and a roll of wrapping wire. And it looks way cleaner!

I'm going to put all buses at the bottom side, and use top side only for power rails & glue logic wiring.

Also reserving some space for EEPROM (rightmost socket), SID (bottom-right), & VIA (bottom). I'll mount 2004 LCD separately, probably in a daughterboard fashion. But I really want to keep all chips exposed, it's so satisfying to simply be able to observe them.

I'm also planning to add a bunch of dual 7-segment indicators with GAL-based hexadecimal decoders to be able to observe what's going on at the data & address lines.

[BigDumbDinosaur]

and3rson wrote:

I'm going to put all buses at the bottom side, and use top side only for power rails & glue logic wiring.

What about the bypass capacitors?

[and3rson]

BigDumbDinosaur wrote:

and3rson wrote:

I'm going to put all buses at the bottom side, and use top side only for power rails & glue logic wiring.

What about the bypass capacitors?

Just finished adding them, photo was taken before I've added them

[BigDumbDinosaur]

and3rson wrote:

BigDumbDinosaur wrote:

and3rson wrote:

I'm going to put all buses at the bottom side, and use top side only for power rails & glue logic wiring.

What about the bypass capacitors?

Just finished adding them, photo was taken before I've added them

Construction notes...

Dual-wipe DIP sockets are significantly cheaper than the machine-tooled ones you have on your board. In prototyping, there is no advantage to using machine-tooled parts, and in production, sockets are usually avoided where possible for reliability and cost reasons. You’ll find it easier to insert chips into dual-wipe sockets than into machine-tooled ones—pin alignment won’t be as critical.

In the future, you should consider the use of a half-can oscillator, which is functionally a DIP-8 package, but with four pins. Size-wise, it’s about 60 percent the size of a full-can unit of the type you have on your board. Sockets made specifically for half-can oscillators are readily available.

There are more-compact ZIF sockets that are available. Here’s the one I use.

[floobydust]

In addition to BDD's construction notes...

the ZIF socket for the EEPROM. I generally use a machine-tooled socket on the board and plug the ZIF socket into it. You get the benefit of easy chip removal/insertion during development and can reuse the ZIF socket on later projects.

[barnacle]

As a practical leg-defensive approach: I use a chunky zip socket on the programmer, but a standard socket on the board (apart from anything else, for space reasons). But I keep a sacrificial socket on the eeprom; neither the programmer nor the board socket object and it means the eeprom pins don't get accidentally bent with all the insertion and removal.

Neil

[and3rson]

Using machine-tooled sockets with a ZIF socket is actually a cool idea, I didn't think about it. It will definitely reduce the footprint on the board also make it easier to squeeze extra caps/wires underneath. I'll try it!

In the meantime, I've updated my schematic to pass all ERC checks and came up with a version that I'll attempt to make a PCB of.

My 4x W65C02S have been shipped now, so I'll have them really soon - I hope! I've decided to include 2004 LCD & 6522 VIA in my "beta" PCB prototype, and I'll still use my perfboard for testing the basics - 6502+RAM+ROM.

[daniMolina]

Just once thing I once fell for. The most standard LCD text displays (All based on the Hitachi HD44780) have an active high Enable line. They are also quite slow, they will probably struggle at 1Mhz. In my SBC (viewtopic.php?f=4&t=5907), I bitbang the LCD interface with a VIA so I can run the CPU as fast as I need to.

[BigDumbDinosaur]

and3rson wrote:

In the meantime, I've updated my schematic to pass all ERC checks and came up with a version that I'll attempt to make a PCB of.

Looks as though it ought to work.

[and3rson]

So I spent a ridiculous amount of time trying to route the PCB manually, and I eventually gave up and used DipTrace to auto-route things for me, because what the hell, it's just a prototype. (I think this project will actually never leave "prototype" stage, haha).
Also I've managed to squeeze everything within 10*10 cm footprint! That will save me some bucks.

My friend offered me some help with some improvements (including teardrops & copper pours), so that's what we'll try to do before printing.

Anyway, I know auto-routing is not perfect, there might be crosstalk and stuff, but I think it *should* work for my 1MHz device. I'll still be making another one with SID, EEPROM, & ACIA some time in the future - but for now, I just can't wait to order my bare-minimum first PCB ever!

[BigEd]

Looks like a good result to me. Each year that passes, I'd imagine autorouters get just a little bit better.

[GARTHWILSON]

and3rson wrote:

My friend offered me some help with some improvements (including teardrops & copper pours), so that's what we'll try to do before printing.

Anyway, I know auto-routing is not perfect, there might be crosstalk and stuff, but I think it *should* work for my 1MHz device. [...]

Copper pours absolutely do not qualify as a ground plane.  They won't add any benefit unless you have lots of vias from the edge of the pour to a real ground plane, especially next to signal vias.  You could look up "coplanar waveguide" and "via fence" but the speeds of current 65xx OTS parts don't warrant going to that extent.  There is a way to use them to supplement real planes; but if they're not done correctly, they can actually make things worse, according to experts in the field like Rick Hartley, Eric Bogatin, and Suzie Web whose lectures you can see on Altium's YouTube channel.

In your case, I wouldn't worry about it.  I think you'll do just fine as-is.  For one thing, your board is kind of small for the edge rates involved.  I would do a ton of manual clean-up, but that's partly just me being kind of OCD about this stuff.  Do provide the shortest path you can between the ground pin of each IC and those around it, and of course to your bypass capacitors, and pay special attention to the Φ2 clock distribution, and you won't have any trouble.

Good luck.  We'll look forward to a happy report of a working board.

[Dr Jefyll]

and3rson wrote:

So I spent a ridiculous amount of time trying to route the PCB manually, and I eventually gave up and used DipTrace to auto-route things for me

It's not bad! And I've created a monochrome version of the image.

I notice the headers attaching to VIA Port A and Port B are only 10 pins each. I'd suggest 14 or even 16 pins each so you can connect a ribbon cable to an external device and supply the device with power, ground and perhaps even an extra signal or two.

I guess you're anxious to proceed. But if you decide to do another pass on the design, you could save some space by using a smaller oscillator, if available. Alternatively, the oscillator could be relocated. Right now the width of the board (from west to east) is consumed by...

• oscillator, CPU, RAM, ROM, VIA. Instead, you could try...
• ROM, RAM, CPU, VIA

The ROM (in its ZIF socket) is comparatively bulky, which is one reason I think it might do well at the edge of the board. Half of that extra width can hang over the edge! Oh, and I was thinking the CPU would be oriented with pin 1 toward the north, whereas the RAM, ROM and VIA would have pin 1 toward the south. This will tend to untangle some of the bus lines, but maybe with the auto-router you won't worry about that. Still, it'd be interesting to see what it would produce if you start by arranging the chips as I suggest.

Whether you do or don't reorient the chips, I would still consider moving the oscillator. With the extra width that's freed up, maybe those two headers for Port A and Port B could snuggle up broadside right next to the VIA instead of being pushed off the end. Just an idea... Good luck with the project, and have fun!

ps- and as Garth says, you needn't bother with the pour -- it is not a ground plane.

-- Jeff