6502.org

I think I see a fly in the ointment. If you are going to use a 6530-004, then the I/O is hard coded to be at $6300. That has an alias of $0300 on a 6504. So unless you kept your ram under 768 bytes, there is a conflict.

The schematic I found says it's expected to be found at $6E00. That's consistent with requiring A13 high to select CS2. My decode logic should work as an equivalent to that.

Conversely, if you use a 6532 and separate ROM, you could patch the original monitor code to suit the memory map actually implemented.

Right, $6E00 - I meed a better schematic and better eyes. Yeah, that should work great for 2K RAM.

Sorry for the false alarm.

I like your idea of using a 6532 and a ROM - these I have. This provides more flexibility too. Anyone have an editable version of the TIM source?

There seems to be this, linked from here.

Thanks!

Double-checking, I see that there are some differences between the 6530 and the 6532 besides the lack of a ROM in the latter. For a start, the pinout is completely different. The select pins also have different meanings and polarities.

More subtly, the 6532 adds the ability to trigger an interrupt on a PA7 input transition, and the I/O register map is modified to accommodate that, requiring the "Write Timer" locations to have A4 set (the 6530 ignores A4 in the I/O section). This may require attention when modifying the monitor ROM, even if the memory map is laid out the same way otherwise.

I'll leave the problem of remapping the vector area between two different chips to you…

Yes I do have a 6530-004, in fact two of them just arrived yesterday. If I did use the 6532 then I think things would be easier, but the idea was to use the TIM kit set (just a 6530 really) as the basis of the system so that I didn’t need an EPROM.

I had accounted for the aliasing every 8k, that is expected/normal with the reduced address range, but my attempts at address decoding for the already preconfigured 6532-004 did not go well. It assumes a 64k bus and works well with that, but the abbreviated bus is more difficult. Luckily the address decode requirements for 64k did not result in any conflicts for 8k, so it’s not impossible, just difficult.

I like your idea of using a ‘138 Chromatix, I hadn’t considered that. I’ll have to work it through and see if it does indeed work with the pre-programmed decode logic of the 6530-004. Until you mentioned that I was ready to give up and just use a 6502, as it would be so much easier.

You should be able to implement my decoding scheme with just a '138 and an '00, in either the 74LS or 74HCT series. The CS2 equation is a plain 2-NAND, while the CS1 equation is a 2-OR which can be implemented using the three remaining 2-NAND gates in the '00.

However, the old 2114 RAMs present a timing complication, because it's quite possible to have a glitch on the /CE line while the address lines are changing and /WE is asserted. You therefore want to have a Phi2-qualified /WE signal to the RAM (but not to the 6530), to prevent writes to other locations potentially corrupting RAM. This requires another pair of 2-NAND gates (or one 2-NAND and an inverter). It's up to you whether you want to use one '00 and one '04 (using only half the available gates on each), or two '00s (leaving two gates spare).

I spent a couple of hours yesterday getting the address decoding sorted out. Cromatix's idea of including a '138 really helped out. In the original schematic there is a 7442 to decode the RAM addresses. This is a BCD to decimal decoder, so quite a creative use to use it for address decoding. It turns out if you fully commit to the '138 it works out really well, I've got everything decoded with no aliases at all, and 3 1k sections decoded on the expansion connector.

I'm planning on putting this board to use with an EPROM programmer card, so the expansion connector will be useful.

For the rest of the schematic I've tried to remain as close to the original suggested design. I've omitted the current loop interface as that's not much use today, and I've hooked up the parallel interface to a DE25 port that should, if I have wired it correctly, interface to a PC parallel connector and allow for data download.

The reset is manually operated, no power on reset here. There are some changes as I've doubled the RAM using 2114's instead of the 2111's in the original design. I've qualified the write on PHI2 as Chromatix points out too, hopefully I've got that right.

There are quite a few unused gates (on the right). This is mainly in the LM1488 and LM1499. They were used more in current loop interface so there is a bit left over. It's a bit wasteful, but it's probably close to what an early 1980's design would do for serial. We have a lot of better options today.

Not sure that basic will fit in this address space, VTL02 looks nice though and seems to meet the size requirements.

The expansion connector will be a card edge connector. It looks like gold is too expensive, but it would look nicer.

This is a first draft of the full schematic, I still have to check it for errors. I'm reasonably confident that the address decode is correct, but I might be tempted to breadboard it just to confirm that it all does work. I hope PDF is an ok format, if not I can convert and upload as something else.

Looks nice and clean. Using a MAX232 might help simplify your serial implementation (lower chip count, single supply). Unless you are after period specificity, I don't think there would be anything hard in the competition rules against it.

For the qualified write, I think you want the inverter on the R/W signal going into the NAND gate rather than on the output. That way the qualified write will be low when Phi2 is high and R/W is low.

If you do have the plus and minus supplies, the 16-pin MC145406 further reduces the parts count. It has three line drivers and three line receivers, and does not need the external capacitors for charge pumps like the MAX232 needs.

The LM1488/LM1489 pair is quite wasteful as it’s two chips for only two pins, but it is in the original design. Max232 is a lot easier, but wasn’t released until 1987 so for this design it’s a bit new. I’m using the MC145606 in another design, so MC145406 would be a good candidate, could be a good candidate, but it looks like it may be 1987 vintage as well, so not really fitting with an early 80’s design.

A quick update, I'm basically waiting for parts at present. The current Covid-19 issues are causing some delays and issues, but also some of the parts are a little hard to find. In particular finding a 1 MHz crystal in HC49/U (large can) was quite a challenge. There is one apparently on it's way to me now, but it's way more expensive than a full oscillator, so you're better off avoiding some of these older parts if you can.

One supplier of parts tried to charge me extra for delivery. Web site said free delivery but on checkout I was charged US$18 for shipping. After a little thought I just paid it, but then they sent me an email message saying my address was rural delivery (it's not) and I needed to pay an extra US$30 for that. I cancelled the order and re-ordered through an eBay seller that I think it quite reliable. He's sending me the parts I need for US$7 shipping.

The MC1488, MC1489's were also a little hard to find. Apparently I'm being sent ceramic versions of these.

I have the power supply, all the other parts are ordered, but who knows when they will arrive. And then, as is said around here, I can see if it goes or blows.

Fitting everything in a 100mm x 100mm board was quite challenging. Looking at it now it looks like there is space left over, but the routing wasn't easy. The expansion connector is based on the Apple II, but with PHI2 added. I'm working on an EEPROM programming board that will hopefully make this a useful device rather than just a historical curiosity.