Avoiding bus contention if you were to accidentally write to an EPROM address, with a minimum of parts, seems to be the main focus on this one. I would say however that such writes are not really a concern. The program-bug conditions that would make them happen will be rare and probably be encountered only during program development and then fixed, and be at too low of a duty cycle to cause any hardware damage, and the bug would probably make your program crash anyway even with the hardware protection against writing to EPROM.
cbmeeks is only going for 2MHz max here though, so there's not really any need to select the EPROM before phase 2 and get all the access time that becomes available that way unless the EPROMs are antiques of 250ns or slower. EPROMs will produce the first roadblock as you turn the clock rate up though.
Also, the simultaneous assertion of /CE and /OE on the EPROM will have some negative effects on performance.
It's best if /CE is asserted as soon as the address bus goes valid with an EPROM address, even though Ø2 is still low. /OE should only be asserted when Ø2 goes high. Controlling both inputs from a single source, as shown in the above circuit, narrows the window of opportunity to read the EPROM before the end of the bus cycle. This because it takes time for the EPROM to come out of the high-Z state and connect to the bus, which can only occur when both /CE and /OE have been asserted. Asserting /CE is what "wakes up" the device from low power mode and typically takes the most time. Hence the suggestion that /CE be asserted as soon as a valid address exists. Reading the device should be gated only with /OE.
Perhaps the circuit could be modified to assert the ROM chip enable, like so;
Does anyone know by how much PHI1 leads PHI2, please? I'm not sure I understand the timing diagrams in the Datasheets.
TIA... Mike
Last edited by Michael on Thu Jul 08, 2021 5:21 am, edited 2 times in total.
Does anyone know by how much PHI1 leads PHI2, please? I'm not sure I understand the timing diagrams in the Datasheets.
WDC no longer guarantees or measures the delays between Φ0 (ie Φ2 in), Φ1, and Φ2 (ie Φ2 out), and they don't recommend using Φ1 or Φ2 out. I think that's silly, since the circuits are still there and they work and yes you can hang an RC or a crystal on the processor itself and it will still work; but since they don't guarantee it, we're on our own if we do it. If they don't recommend using them, they could use those pins for something else useful. Anyway, I looked at an older data sheet and saw that the guaranteed max delay between Φ0 and Φ1, and also the guaranteed max delay between Φ0 and Φ2, for the 14MHz W65c02S, was 22ns. It's strange that they would have the same number for both, as I think that internally Φ2 (out) is derived by running Φ1 into an inverter and then using its output for Φ2 (out).
Does anyone know by how much PHI1 leads PHI2, please? I'm not sure I understand the timing diagrams in the Datasheets.
The clock outputs on the 65C02 are there to facilitate the retrofit of the 'C02 to systems that used the NMOS 6502. As Garth noted, WDC does not (and has not for a long time) tested the timing characteristics of the clock outputs of their 65C02 production parts. Use of those outputs is not recommended in new designs.
Note that the 65C816 does not have clock outputs—only a clock input exists. If you are designing something in which you eventually may want to install the 65C816 and need a two-phase clock you'll have to roll your own. The below circuit uses a TTL can oscillator and one section of a 74ABT74 flip-flop to produce a two-phase clock with a very sharp rise and fall and no lead or lag between outputs.
EPROMs will produce the first roadblock as you turn the clock rate up though.
