BigDumbDinosaur wrote:
Also, the simultaneous assertion of /CE and /OE on the EPROM will have some negative effects on performance.
It's best if /CE is asserted as soon as the address bus goes valid with an EPROM address, even though Ø2 is still low. /OE should only be asserted when Ø2 goes high. Controlling both inputs from a single source, as shown in the above circuit, narrows the window of opportunity to read the EPROM before the end of the bus cycle. This because it takes time for the EPROM to come out of the high-Z state and connect to the bus, which can only occur when both /CE and /OE have been asserted. Asserting /CE is what "wakes up" the device from low power mode and typically takes the most time. Hence the suggestion that /CE be asserted as soon as a valid address exists. Reading the device should be gated only with /OE.
Perhaps the circuit could be modified to assert the ROM chip enable, like so;
Attachment:
Beattie Notes.png [ 85.97 KiB | Viewed 248 times ]
Does anyone know by how much PHI1 leads PHI2, please? I'm not sure I understand the timing diagrams in the Datasheets.
TIA... Mike
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EPROMs will produce the first roadblock as you turn the clock rate up though.
