How do we handle the loss of 5V CPLDs?

[GARTHWILSON]

The data sheet rates the W65C02S for 14MHz @ 5V and 8MHz @ 3.3V. I suspect that the reason is that for a given wafer process, at the lower voltages, the transistors' gate voltages are not as high, so the transistors don't get saturated as well, so it takes longer to charge up the capacitances. In an RC time constant, the R is higher at the lower voltage, and the C may be higher too because of thinner depletion regions, making for longer time constants. We know that the processor can typically go much faster than spec'ed if the supporting parts can operate adequately with the reduced timing margins.

[BigEd]

Bear in mind when comparing datasheets with experience, that datasheets aim to cover the worst case for
- voltage
- temperature
- process variation
So, even the 5V would be nominal, and testing should be at -10% or whatever is the specified margin. Likewise, test at high temperature. And finally, the consumer cannot explore the effect of process variation, but the vendor must protect themselves: from one lot to the next, one wafer to the next, and different die across a wafer will all have some variation.

Oh, and of course you need to check the worst path on the chip. That might be something like an untaken branch crossing from 7FFF to 8000. Or it might be a decimal subtraction of AA from 22 being stalled by RDY. Even a functional test suite is unlikely to hit the worst case path: it takes some expertise to write test programs for CPUs.

[Dr Jefyll]

scotws wrote:

When does the effect become noticeable?

Any drop in supply voltage has an effect -- is that what you're asking? The logic switches a little more slowly, and that impacts the timing budget. To some extent you can get away with that -- it depends on how much extra timing margin there is. When the margin goes negative you have a problem. The computer will fail if the logic can't keep up with whatever clock speed you've chosen. The upshot is, the supply voltage directly relates to the potential maximum clock rate -- at least in theory. [D'oh! I didn't notice others had posted while I was typing. But Ed has given some good insight on the topic of margins.]

Windfall wrote:

Both use a 14 MHz rated W65C02, although a) can also employ a W65C816. a) is a DIP, runs at 5V, and up to 20 MHz (with 20 ns SRAM). b) is a QFP, runs at 3V3, and up to 24 MHz.

It does seem odd, John. And congrats on the nice work, btw! I suppose if you wanted to get to the bottom of this voltage/speed question you could find the max clock speed for the 5V machine, then run the test again on the same machine but powered by 3.3V. Edit: Hmmm, I guess the ULA and what it attaches to make it tough to power that machine with 3.3V.

-- Jeff

[scotws]

GARTHWILSON wrote:

The data sheet rates the W65C02S for 14MHz @ 5V and 8MHz @ 3.3V.

So for those of us interested in size instead of speed, we should be able to run a 65816 at 3.3 V if we stay at 8 MHz, thus granting easy access to (say) the AS7C316096A 2 MB 10 ns SRAM for about 20€ (http://www.mouser.de/new/Alliance-Memor ... efastsram/)? The size difference alone is pretty impressive.

[GARTHWILSON]

It makes sense, although I always like to connect a variable-frequency oscillator (VFO) to it and see how high it can go before it starts having problems, then back it down a bit to have some margin for hotter conditions or whatever. With a really good design, you might find you can go quite a bit faster than the spec.s let on.

[scotws]

And I just checked: The Xilinx XC9572 that is used for the 65SPI can be used with 3.3 V as well (http://www.xilinx.com/support/documenta ... /ds065.pdf). So I guess I go throw out my design (again) ...

[BigEd]

Just to note that some of these EOL XC9572 are for sale on ebay UK at present:
http://www.ebay.co.uk/itm/XILINX-XC9572 ... 3aad7dbdf3
In case anyone wants to pick up a few as a last time buy. Can't vouch for the seller myself but we'll soon see. Thanks to richarde for the tipoff.

Edit: richarde notes that the PLCC parts are attractive because it's easy to get through-hole sockets. The 5V-tolerant XC9500XL family is still available, but in other packages. (Although 5V tolerant, you'll need a 3V3 supply)

[BigEd]

Just had a quick look for in-production 5V-tolerant programmable parts. Found these:

Altera MAX 7000, MAX 9000 CPLD
https://www.altera.com/products/general ... index.html

Atmel ATF15xx CPLD (some but not all support 5V operation. Maybe as slow as 25ns)
http://www.atmel.com/devices/ATF1508ASL.aspx

Lattice ispMACH4000ZE FPGA (needs eeprom, takes milliseconds to configure at power up)
http://www.latticesemi.com/Products/FPG ... 000ZE.aspx

Xilinx XC9572XL CPLD
Still active product, according to digikey. Down to 5ns propagation

[LIV2]

I've been playing around with the XC9572XL lately myself, one thing to note is that there must be no inputs at 5V before the 3V VCC is stable.
Another thing is that while it's 5V tolerant, the output high voltage isn't high enough for 5V CMOS like the 65C02, it seems to work on my system but noise is a problem
Hasn't been a problem for me so far, I've just been using a buffer between the CPLD and the bus, but I might try to pick up some Altera Max 7000's and use those instead. thanks for the posts!

[hoglet]

LIV2 wrote:

I've been playing around with the XC9572XL lately myself, one thing to note is that there must be no inputs at 5V before the 3V VCC is stable.
Another thing is that while it's 5V tolerant, the output high voltage isn't high enough for 5V CMOS like the 65C02, it seems to work on my system but noise is a problem

Which type of 65C02 are you using?

I believe the Rockwell 65C02 uses TTL levels (i.e. Vin_low_max 0.4V, Vin_high_min 2.4V), which could be fine when driven with 3.3V.

Dave

[LIV2]

Unfortunately I'm using a WDC 65C02 with WDC ACIA & VIA's.

What's the best way to deal with bidirectional 3.3V to 5V CMOS at 5Mhz+? Pullups and Tristate the inputs of the CPLD instead of setting them high?

[cbscpe]

All my designs are 5V only and I use the ATF1504/8 as suggested by BDD at the beginning of this thread. The ATF1504 has 64 macrocells and the ATF1508 has 128 macrocells. For a 6502 system the ATF1504 has sufficient resources. However when building a 65C816 base system with 24bit addresses the ATF1508 is the better choice. Else one of those bidirectional level shifters mentioned at start of this thread should do the job. I try to avoid level shifters it's just another IC and you need to route more signals and place all 3V devices on one side and the 5V devices on the other.

[BigDumbDinosaur]

cbscpe wrote:

For a 6502 system the ATF1504 has sufficient resources. However when building a 65C816 base system with 24bit addresses the ATF1508 is the better choice.

Interestingly, I had ample logic resources available with the ATF1504 in POC V2, once I let the fitter decided which I/O pins should be attached to what. However, all available I/O pins are used and in fact, a couple of features I was hoping to integrate had to go by the wayside because I had no place on the CPLD to make connections.

The next design will go with the ATF1508 so as to gain more I/O pins (64 uncommitted with the 1508 vs. 32 for the 1504). I did POC V2 with the 1504 so as to keep the PCB size within the Express PCB Proto-Pro limits.

[cbscpe]

BigDumbDinosaur wrote:

Interestingly, I had ample logic resources available with the ATF1504 in POC V2, once I let the fitter decided which I/O pins should be attached to what. However, all available I/O pins are used and in fact, a couple of features I was hoping to integrate had to go by the wayside because I had no place on the CPLD to make connections.

That is exactly the problem. I always ended with too few available pins when putting all the GLUE into one ATF1504AS for a decent 6502 system. For a 65C816 system you need at least the data bus, a reasonable number of the address bits for decoding, this already uses at least 16 PINS. In addition you need PHI2, CLK, RESET, RDY, RW, the memory interface requires at least 6 PINS for 512kbyte. This already uses 27 out of 32 PINS. This leaves you with 5 pins for the IO select lines and the ROM select line. This is rather for a minimal 65C816 system. I always had to add an additional IC for some minor features. Unfortunately the PLCC-68 version of the ATF1504AS with more IO Pins is no longer available. But a a ATF1504 in PLCC-44 plus another IC requires almost as much space as a ATF1508 in PLCC-84. You don't save any PCB space using a ATF1504. If space is critical then I would rather go with a ATF1508 in TQFP-100. With this you use very little space, a lot of logic and 80 IO PINs.

[BigDumbDinosaur]

cbscpe wrote:

For a 65C816 system you need at least the data bus...

Not the entire data bus. POC V2 has 1 MB of RAM, so I only needed D0-D3 to generate A16-A19. Coincidentally, the HMU has four bits, three for memory map control and one for write-protecting or write-enabling the $00E000-$00FFFF range of RAM. So I was able to avoid having to connect D4-D7, saving some pins.

However, as you note, the ATF1508's higher pin count is necessary for a more elaborate system. The PLCC68 form of the 1504 would be nice, but oh well.