6502.org

Forgive me if I'm saying things you already know. Since you're rather new here, I don't know how much you know about different aspects, although obviously you've put a lot more thought into memory protection than I have. Of all the knowledgeable people on the forum, each has strengths that others don't have (which I guess is part of the reason for a forum, huh?). We all wish each other (including you) success of course.
Ah yes, regarding the pattern. WW pins (of single in-line or DIP, not a square PLCC socket) can however go into all the solderless breadboards I've used-- with care. I've never damaged a solderless breadboard with .025" square posts, but it's probably borderline. I don't do any computer work with solderless breadboards though, as they're the worst of all worlds for that, regarding inductance and its many bad effects on fast digital lines. Fortunately (in that regard), you said you're using Rockwell and GTE parts which I don't think ever came in more than 4MHz. With slow parts at 1MHz, you can get away with murder. But turn up the speed, or even use faster parts at slow clock rates (ie, the output slew rates are faster when they do change state), and you can get into trouble. In the computer I mentioned above that took about 2mA for the entire computer (including LCD), I did initially breadboard that with solderless breadboard, but it was with 2MHz parts, and spent most of its time at 170kHz. Make sure you look at the sticky topic, "Techniques for reliable high-speed digital circuits" and the "Construction: Avoiding AC-Performance Problems" page of the 6502 primer.

Make sure your 6522 selects are not qualified by phase 2. They, like R/W, must be valid and stable a specified minimum amount of time before phase 2 goes up. (I found out the hard way.)
All the SRAMs I've worked with simply ignore OE\ when WE\ goes down. IOW, they will definitely not try to put data out on the bus when they're supposed to be taking data in to write.

If you find a source of 74ABT688 (or '521-- same thing), please let us know. I have not been able to find any, in any package. 74AC is the fastest I've been able to find a '688 or '521 in.

Ed is right. The fact that the W65C02S has a static core does not mean you are free to violate the setup/hold times for the RDY signal. According to the data sheet the RDY signal is sampled on the negative edge of the PHI2 clock, so it needs to be stable at that point.

If you don't adhere to the setup/hold times, you can cause undefined behavior. This could happen if the RDY input splits in two (or more) paths inside the device, and each of those paths leads to a different flip flop. Due to timing differences, one flip flop could capture RDY when it's low, and the other could capture it when it's high, leading to a bad internal state.

Edit: In addition to the problem with multiple paths giving different interpretations to an input, there's also the issue of metastability when setup/hold times are violated.

There's nothing to forgive... I've been lurking here for a while and I'm aware that your advice (from all of you, that is) is very valuable. Even if you say something I already know, it's always good to have a reminder, and could be very helpful for another newcomer arriving here, too.

It goes without saying, in a nice forum like this one, everybody wins!
I usually don't like to force things... if it doesn't fit easily, I won't push any harder, just in case... so that's probably the case.
I've been cursing on them for decades and that's for analog work! But maybe my theoretical background is not that strong, so the are very valuable for experimenting things -- once one is aware of their limitations.

This far, my current 6502 computer is on a, ahem, solderless breadboard. But that's going to change, obviosuly.
Now I'm using a 1 MHz 65SC02 from GTE, and a 2 MHz Rockwell VIA. The EEPROM (2816) is rated 250 ns and the SRAM... whatever NEC means by -3 for their 6116 equivalent! (it looks like 150 ns -- huh, NMOS??? ) But quite surprisingly, this combo is able to run rock steady at up to 4.6 MHz -- and that's on a breadboard! The extremely simple decoding is mostly the "culprit". On the other hand, I'm having problems with a thight, soldered circuit at 1 MHz... but I'll start another thread for that.
Highly recommended reading! I feel I should get into the world of WW...
Yes, I did -- read your advice a while ago. But you're doing well pointing this again, it's an easily overlooked issue which could be difficult to troubleshoot!
Certainly, and I usually tied OE\ to ground; but with my protection circuit, it could happen that the CPU is trying to write but WE\ does not go down (because the protection circuit gets in the way and disables it).

Anyway, I think the recommendation from BDD of qualifying reads (thru OE\) with ø2 makes a lot of sense... especially if the system is running at a much slower speed than its components are rated -- say, 1 MHz with 4 MHz parts. If a fast CPU is going to write to RAM, it may put the data on the bus quite early in the (slow) cycle, probably well within ø2 low. And with fast memory and fast decoding, the SRAM may put the supposedly read data by then because WE\ is still high -- it won't be asserted until ø2 goes high. Thus, a brief bus contention will happen...
I'll do Anyway, I think I'll stick to AC for a while.

Now I'll post about my system(s) in other threads... Cheers,

MTBF is a numbers game. Until you reveal some numbers, we can't possibly be impressed with your experiment.

I've heard 65xx family device have had application in Medical Devices. I wonder if you'd like to have a pacemaker implanted -- if the team that designed it shared your views regarding timing specifications!

Dr J

Fortunately they will follow more-stringent testing and approval requirements for medical equipment than they do for drugs! As one doctor put it, 90% of prescription drugs belong in the toxic-waste dump.

There's part of my designs that have been going into aircraft for the last 20+ years that uses a transistor in a way you won't find in any textbook though, and supposedly can't work, yet it has never shown itself to be unreliable. I used it for years before finding (as I suspected) that I'm not the only one who has discovered the effect. If it were to fail though, it would just make communication and entertainment a bit irritating. The plane would not stop flying.

Well, the timing diagram shows that RDY should be stable in the setup/hold interval around the falling clock edge. This is typically all the documentation you need. However, you are right about the IRQB, NMIB and RESB signals, which would be assumed to be completely asynchronous wrt to the clock.

To be safe, I would stick to the documented setup/hold times for RDY, or ask WDC to clarify. Given the fact that RDY affects many more flip flops inside the device as the other 3 signals, there may well be a difference.
That would depend on how many combinations you've tested. It could be that the ill effects are subtle, and only occur when certain types of instructions are executed, and only once in 10 million times.

But you don't know that. There could be circumstances where parts of the device respond to the wait state one cycle earlier than other parts. For instance, the PC incrementer could see that the RDY was high, and increment the PC, but the carry flag updater could see that RDY was low, and not update the carry flag.

That's what I thought you were saying and I agree.
If you want to put a toggle switch on RDY and then toggle it any time you want then there will be times it will not meet setup time but will then be read on the next cycle just like IRQ. Of course setup time would be taken into account in an actual design.

No sweat, I actually think you explained fairly well. And, to be honest, I would've agreed with you if you'd asked me earlier. But Arlet's first post set me straight.

There's lots of intersting reading if you follow the link he provided. MTBF is very much part of that vocabulary, btw.

cheers,
Jeff

Interesting - I hadn't noticed that the interrupt inputs have the same timing description. Perhaps we do tend to assume that they are asynchronous inputs - although in many designs they are in fact produced synchronously by other devices on the same clock.

In the NMOS 6502 we do see a particular front-end stage on the chip for the interrupt inputs, but not for RDY. See for example viewtopic.php?p=25814#p25814 - the best one can do is have high-gain stage, because the usual solution of multiple flops wouldn't fit the function.

By coincidence, I've just read a bit about the original IMPs (nodes on the Arpanet) which were variant Honeywell 516s. It seems they had metastability problems, down to a design defect, with an MTBF of hours to days. The people at BBN built a test circuit to irritate the interface enough to make the problem observable on a 'scope. (Computing in the Middle Ages: A View From the Trenches 1955-1983)