6502.org

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module vga_char
(
    //input  wire     RESETb,     // Reset bar
    input  wire     VGA_CLK,    // 25.175 Mhz clock
    output reg[9:0] HC,         // Horizontal counter
    output reg[9:0] VC,         // Vertical counter
    output reg      CHAR_LD,    // Character load
    output reg      BLANK,      // Blank bar (output disable)
    output reg      HSb,        // Horizontal Sync bar
    output reg      VSb,        // Vertical Sync bar
    output wire     OUT_CLK     // Delayed clock
);

// Resultion is for 640x480 @ 60Hz

/*
 * 0       48                     688     704
 * | back  | VISIBLE_AREA_PORTION | front | sync  |
 * | porch |                      | porch | pulse |
 */


// Operational constants
parameter HORZ_TOTAL     = 800;
parameter HORZ_RES       = 640;

parameter HORZ_BACK      = 48;
parameter HORZ_SYNC      = 96;
parameter HORZ_FRONT     = 16;

parameter HORZ_SYNC_START = HORZ_RES + HORZ_FRONT;
parameter HORZ_SYNC_END   = HORZ_TOTAL - HORZ_BACK;

//parameter HORZ_VIS_START  = HORZ_BACK - 1;
//parameter HORZ_SYNC_START = (HORZ_TOTAL - HORZ_SYNC) - 1;
//parameter HORZ_VIS_END    = HORZ_SYNC_START - HORZ_FRONT;

parameter VERT_TOTAL      = 525;
parameter VERT_RES        = 480;

parameter VERT_BACK       = 33;
parameter VERT_SYNC       = 2;
parameter VERT_FRONT      = 10;

parameter VERT_SYNC_START = VERT_RES + VERT_FRONT;
parameter VERT_SYNC_END   = VERT_TOTAL - VERT_BACK;

//parameter VERT_VIS_START  = VERT_BACK - 1;
//parameter VERT_SYNC_START = (VERT_TOTAL - VERT_SYNC) - 1;
//parameter VERT_VIS_END    = VERT_SYNC_START - VERT_FRONT;

wire horz_valid, vert_valid;

always @(posedge VGA_CLK)
begin
    if (HC == HORZ_TOTAL - 1)
    begin
        // End of horizontal line, increment vertical
        HC <= 10'd0;
        if (VC == VERT_TOTAL - 1)
        begin
            VC <= 10'd0; // End of vertical, reset
        end
        else
        begin
            VC <= VC + 1;
        end
    end
    else
    begin
        HC <= HC + 1;
    end

    horz_valid <= (HC < HORZ_RES);
    vert_valid <= (VC < VERT_RES);

    HSb <= (HC >= HORZ_SYNC_START) && (HC < HORZ_SYNC_END) ? 1'b0 : 1'b1;
    VSb <= (VC >= VERT_SYNC_START) && (VC < VERT_SYNC_END) ? 1'b0 : 1'b1;

    BLANK <= !(horz_valid && vert_valid);
end

assign OUT_CLK = HC[0];

always @(posedge OUT_CLK)
begin
    CHAR_LD <= !BLANK &&     // Load only when not blanking
               HC[3:1] == 0; // and on zero pixel
end

endmodule

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`timescale 1ns / 1ps

module top_module
(
	input CLK,
	output reg HSYNC,
	output reg VSYNC
);

reg [11:0]hCounter = 'd0;
reg [9:0]vCounter = 'd0;

always @(negedge CLK)
begin
	if(hCounter >= 'd0 && hCounter < 'd95)			// Horizontal Sync
		HSYNC = 0;
	else
		HSYNC = 1;
	
	hCounter = hCounter + 1;
	
	if(hCounter == 'd800)						// End of horizontal line
	begin
		hCounter = 'd0;
		vCounter = vCounter + 1;
	end
	
	if(vCounter >= 'd0 && vCounter < 9'd2)			// Vertical sync
		VSYNC = 0;
	else
		VSYNC = 1;

	if(vCounter > 'd525)							// End of vertical lines
		vCounter = 0;
end

endmodule

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// Partial verilog
always @(posedge VGA_CLK)
begin
    // Update counts here.
    BLANKb <= !(HC >= 15); // This won't go low until HC == 17!
end

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// Partial verilog
always @(posedge VGA_CLK)
begin
    // Update counts here.
end

always @(HC[0])
begin
    BLANKb <= (HC >= 15); // Now it goes low on 16 as expected.
end

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nC0 = !C0;
nC1 = C0 & !C1 # !C0 & C1;
nC2 = C0 & C1 & !C2 # !C0 & C2 # !C1 & C2;

Field C = [ C2..0 ];
Field nC = [ nC2..0 ];
C.d = nC;

XOE.d = WP & nC:5 # XOE & nC:[4..6];
RAMWE.d = XOE & nC:6;

SRPE = !CLK1 & C:2 # CLK1 & C:3;