6502.org

My understanding of Chris's design is that the 32k SRAM is divided up so half is for the OS, and then the other half is for the ACIA, VIA and the remainder for use as potential I/O space in a future revision. I'm completely new to all this so my grasp of how it all ties together is almost zero, so take everything I say with a grain of salt!

Looking at the topic for NichH93's issue, it sounds very similar as he was also able to run LIST as well but hit a wall when trying use RUN or text strings. Might be worth picking up another 65C02 to test that option out as my first ACIA didn't work as well, but I chalk that up to it being a used eBay item.

Have you tried to enter a smaller memory count when Basic starts, say 8000 or 4000. Perhaps this will work.

Then there is another problem as the RAM Test in EhBASIC may trash your IO.should be changed toHowever this should not be causing the problems you are seeing.

Just attempted 8000 and 4000 and both would either result in "Memory Size ?" coming up again or system lockup.

The "Memory size ?" prompt will be repeated if EhBASIC thinks the number you entered is too small (below RAM_base) or too large (more than 64k). However it uses already quite a lot of its routines including floating point to determine this. Have you verified that the EPROM was correctly programmed?

The RAM is a 32K chip, but half of the capacity is deliberately unused. That's to simplify the glue logic, I assume.

Basically, the /OE input of the RAM is used as an extra /CS input, and it's driven from address line A14. Of course placing /OE high doesn't really de-select the chip, but it prevents a read from taking control of the data bus -- and that's sufficient. The chip becomes a Write Only Memory anytime A14 is high. That includes $4000-7FFF, which is where I/O appears.


ETA: the same "/OE as an additional /CE" trick is used in Garth's very basic whole-computer schematic. In fact all the glue for memory/I-O is pretty much identical, except Garths' "whole computer in one diagram" design has no ACIA, just a VIA.

Hm, the specs for the oscillator seen in the photo fail to confirm it meets the specified input requirement on a WDC CPU. The oscillator only guarantees 2.4V as a logic high, but the PHI2 input supposedly needs at least VDD-0.4V, or 4.6V. (The VIA and ACIA might supposedly require 4.6V, too -- I didn't check.)

There's a very easy experimental remedy. Just add a pullup resistor (470 ohm? 1K?) from the osc output to +5V. I'll be a little surprised if this clock-voltage thing turns out to be the answer we're looking for. But if it works then you can either leave the pullup in place (although it wastes power) or swap in a more appropriate oscillator. Edit: I notice BDD asked about the oscillator earlier.

Edit 2: creoguy, did we confirm that the Phi2 inputs on the VIA and ACIA also connect to the oscillator (not the CPU PHI2O output on pin 39)?

-- Jeff

The diagram only shows one VIA and no AICAs; but see Note 9 below it. The design allows up to ten I/O ICs with the existing glue logic, and in fact my workbench computer has three VIAs and three ACIAs with this scheme.

I was not able to find a schematic on the OP's linked github pages, to compare. The closest I could find was a text file that apparently KiCAD (sp?) uses to form or interpret a picture, an actual schematic diagram. Maybe there is a picture there somewhere; but this is the top reason I hate github. I never can find what I'm looking for!

Hoglet very thoughtfully posted a PDF version here.
I get that, too. It's gotten so I won't even try unless it's something pretty important.
Pretty slick -- especially considering the existing glue logic is next to none!

I added the pull-up resistor to the oscillator output and it made no difference.
I moved the PHI2 inputs for VIA and ACIA to the oscillator output with no difference in the systems.

At this point, my plan is to wait for the new parts to come in next week to help rule out an IC issue. If the problem continues I'm going to test it out on a breadboard, not my first choice as it has the potential for its own issues, but at least I can easily test out some different glue logic configurations.

Thanks again for everyone's help!

It shouldn't. /WE, /CE and /OE are in the right places, so are the address and data lines. That the address lines (or data lines for that matter) are labeled differently is immaterial for RAM.

BTW, what is this using as a clock generator? I don't see one on the schematic (but I see an oscillator in the picture)?

Never mind - I found your post on the oscillator.

When in doubt, a shotgun approach is always a valid option, even if it's not an elegant one! I got in the CY62256N SRAM chip today and swap it in for the AS6C62256, without changing any of the wiring, and things are now working as expected. That'll teach me to order parts for someone else's design without verifying I'm matching their BOM. The only thing I can think of is the 55ns vs. the 70ns access time was enough of a difference to cause an issue.

Thanks again for everyone's help!

See this post and the ones following it, regarding speed ratings.

With some head scratching, I finally got my Cylon assembly code modified to run in EhBASIC! Now that I have a functioning board, let the fun begin!

Congratulations!