4MB SRAM Module

[GARTHWILSON]

Dr Jefyll wrote:

GARTHWILSON wrote:

• two-layer board's high-speed performance is maximized by unorthodox layout and bypass chip capacitors under the ICs actually embedded in the board for minimum inductance

Capacitors embedded in the board? Cool! That would be underneath an IC, then, right? I've wondered about trying something like that. Care to share the details, and a photo maybe? Sounds like you'd have to use a chisel or router to create a cavity in the PCB material...

-- Jeff
ps- lovely job on the RAM module!

Thanks. I got the embedded-capacitor idea from page 56 of the 4/28/03 issue of Electronics Design magazine. I was going to try to describe it here, then realized I could probably find it online for you. The article is here, and the missing diagram is below. I put the chip capacitors under the ICs (right under the die) instead of in the SMT pads. I left holes with big-enough pads on both sides of the board, then instead of paying for a secondary drilling operation (which I probably should have), I drill out the via so the Vdd and ground are no longer connected by the thru-plating, then put the chip capacitor in the round hole, and solder one end of the capacitor to the top side of the board and the other end to the bottom. 0603 chip capacitors' length is almost the thickness of the board. It would be a little easier to solder if they were slightly longer, or if the board were a little thinner. It's rather labor-intensive, and since you can't see inside once you've soldered, you have to check the capacitance from Vdd to ground after each one you install, to make sure it went up by .1uF and there's no short.

Conventional decoupling (on the right) adds unwanted inductance.

Anyone who knows anything about SMT assembly can see that this method is definitely not suited for efficient automated assembly; but if you want the best performance, well...

I also thought about soldering 0402 chip capacitors to the Vdd and ground leads since they're next to each other in the middle of each side of each IC, but it's just too much work.

In Daryl's last picture above, you can kind of see where two of the capacitors are installed right near the pin header, a half-dozen pins from each end. The other four are under the ICs, each one serving the IC above and below it since there are ICs on both sides of the board. There are vias in the SMT pads, something you cannot get away with for automated assembly since it would allow a gob of solderpaste to squirt through. This is strictly for assembling by hand.

[BigDumbDinosaur]

GARTHWILSON wrote:

Thanks. I got the embedded-capacitor idea from page 56 of the 4/28/03 issue of Electronics Design magazine.

Looks like it would be a challenge for this old dinosaur to assemble. Those things are tiny!

[ElEctric_EyE]

Dr Jefyll wrote:

GARTHWILSON wrote:

• two-layer board's high-speed performance is maximized by unorthodox layout and bypass chip capacitors under the ICs actually embedded in the board for minimum inductance

Capacitors embedded in the board? Cool! That would be underneath an IC, then, right? I've wondered about trying something like that...

That's what I thought too. That the bypass caps were underneath the IC, I almost thought about doing this in the 65Org16 devboard in order to save space on the opposite side of the board. However, it wouldn't have fit unless I modified the IC and bent the pins downward , something I would definately NOT recommend as most SMD's have very thin/delicate pins...

This is an ingenious idea though, putting the cap into a via. Only potential problem is putting too much solder into the via, but as Garth noted, check for a short circuit after soldering each and every cap.
This recent discussion has reminded me to keep distances short when planning traces for bypass caps in my project, something I've not strictly adhered to in my recent designs. I had forgotten the importance of it...

I would've liked to use this concept though I don't think I can take advantage of it on a 4 layer board, with the internal 2 layers being GND and Power.

[BigDumbDinosaur]

ElEctric_EyE wrote:

This is an ingenious idea though, putting the cap into a via. Only potential problem is putting too much solder into the via, but as Garth noted, check for a short circuit after soldering each and every cap.

You could probably do the same thing with a pad, which unlike a via, is not ephemeral.

Quote:

This recent discussion has reminded me to keep distances short when planning traces for bypass caps in my project, something I've not strictly adhered to in my recent designs. I had forgotten the importance of it...

Yes. Short and thick. In my designs, I tend to connect the "positive" side of the decoupling cap to Vcc (this is usually on a 4-layer board) and connect the Vcc pin(s) of the chip to the cap using a thick trace, not the power plane/layer. Hence the only path for switching noise is back to the decoupling cap, helping to minimize propagation to other board areas via the power plane/layer. If possible, I also connect the ground pin(s) of the chip to the ground side of the cap in the same fashion. I did this on my new SCSI host adapter. The 53C94 controller makes quite a bit of (electronic) racket, thanks, in part, to the 48 ma active outputs on all 18 SCSI pins. None of it is showing up in the power and ground layers.

Quote:

I would've liked to use this concept though I don't think I can take advantage of it on a 4 layer board, with the internal 2 layers being GND and Power.

Probably not. Drilling out the plate-through in a via or pad connected to one of the inner layers would most likely break the connection. Plus you'd run the risk of shorting the inner layers together and converting the PCB into a nice (and expensive) bookmark.

[GARTHWILSON]

Quote:

Yes. Short and thick. In my designs, I tend to connect the "positive" side of the decoupling cap to Vcc (this is usually on a 4-layer board) and connect the Vcc pin(s) of the chip to the cap using a thick trace, not the power plane/layer. Hence the only path for switching noise is back to the decoupling cap, helping to minimize propagation to other board areas via the power plane/layer. If possible, I also connect the ground pin(s) of the chip to the ground side of the cap in the same fashion.

I seem to remember reading that two infinite parallel planes in the board have no non-mutual inductance. We can't get them infinite, but keeping parts away from the edge gets close enough. If that's the case, then putting bypass capacitors at each IC should not be necessary. There's some skin effect, but bypassing is not going to fix that. In any case, you would want the ground pins to get to ground immediately, not take an "access road" to a bypass capacitor first. The inductance to ground needs to be minimized as much as possible. If there's no power plane it will be important to get the shortest possible path from the power pins, through the bypass capacitors, to ground.

I don't think I would want to drill out a via for this in a multilayer board if there were pads on the inside layers. It's hard enough to avoid shorts as it is (although I'm getting better at installing the capacitors). Drilling out the via would leave you with .0014" (assuming 1oz copper on inside layers) rings down in the hole which unwanted solder might adhere to and be harder to remove. Just because there's a hole there however does not mean you have to have a pad there on a given inside layer if there's not supposed to be any connection on that layer at that point. Some board manufacturers automatically modify your gerber files to remove pads on inside layers where there is no connection to them.

[BigDumbDinosaur]

GARTHWILSON wrote:

In any case, you would want the ground pins to get to ground immediately, not take an "access road" to a bypass capacitor first. The inductance to ground needs to be minimized as much as possible.

In the case of the 53C94 (the big power-user on the host adapter assembly), all ground pins are grounded directly to the inner ground layer. It wouldn't have been practical (or wise) to tie all the ground pins back to a common point.

In any case, the inductance on a short, thick trace is negligible, in the range of a few pico-henries. I didn't originate the idea—I've seen it used quite a bit on digital designs.

[GARTHWILSON]

data sheet available at
http://gw7.no-ip.com/65xx/modules/WM-1_ ... -30-11.pdf

Update: Make that http://wilsonminesco.com/WM-1_4Mx8SRAMmodule.pdf (I made minor changes for clarification, added the disclaimer, and put the file on my new website.) Update again, after going to the ISSI SRAMs (because the price on Cypress's parts went way up): http://wilsonminesco.com/WM-1_4Mx8SRAMmodule4-23-20.pdf

Edit: A post on the surprisingly minor bus-loading effects it presents is at viewtopic.php?p=18847#18847 .

[BigDumbDinosaur]

GARTHWILSON wrote:

data sheet available at
http://gw7.no-ip.com/65xx/modules/WM-1_ ... -30-11.pdf

From data sheet:

• This is possible with SRAM because as long as data lines go do data pins...

[GARTHWILSON]

BigDumbDinosaur wrote:

GARTHWILSON wrote:

data sheet available at
http://gw7.no-ip.com/65xx/modules/WM-1_ ... -30-11.pdf

From data sheet:

• This is possible with SRAM because as long as data lines go do data pins...

[Edit: Note the updated URL, http://wilsonminesco.com/WM-1_4Mx8SRAMmodule.pdf , as I made minor changes for clarification, added the discaimer, and put it on my new website. Updated after going to the ISSI part: http://wilsonminesco.com/WM-1_4Mx8SRAMmodule4-23-20.pdf ]

continuing the quote, ", it doesn't matter if they get mixed up; the same goes for address lines, and the same goes for CE\ lines." I suppose you can mix up the data lines on other types of SRAM too, but not address lines when addresses in a burst have to be consecutive. It's not an issue with SRAM though, as it truly is random-access.

[BigDumbDinosaur]

GARTHWILSON wrote:

BigDumbDinosaur wrote:

GARTHWILSON wrote:

data sheet available at
http://gw7.no-ip.com/65xx/modules/WM-1_ ... -30-11.pdf

From data sheet:

• This is possible with SRAM because as long as data lines go do data pins...

continuing the quote, ", it doesn't matter if they get mixed up; the same goes for address lines, and the same goes for CE\ lines." I suppose you can mix up the data lines on other types of SRAM too, but not address lines when addresses in a burst have to be consecutive. It's not an issue with SRAM though, as it truly is random-access.

The laugh was about the "data lines go do data pins" phrase. Reads like some of the Chinese to English translations I regularly peruse.

[mdpenny]

Neat design - and it's given me an idea (of sorts)

First, off on a slight tangent (an apologies to those who are already familiar with the following): Acorn produced various accessories for the Beeb in the form of its "cheese wedges" - plastic cases with the back-to-front profile, and about half (I think) width, of the Beeb itself; these could contain a 160mm-by-100mm PCB (and, if needed, a mains transformer coil).

The external Second Processor boxes were of this design, as were the Teletext Adapter (filtered the Teletext subsignal out of UHF TV signals - used for the BBC's "Ceefax" service, among others), and Prestel Adapter.

What occured to me when I saw Daryl's picture of his SBC-4 with the 4MB SRAM module fitted was this: re-purpose the box, mains transformer and connecting cable (to the Beeb's "1MHz Bus" connector) from a suitable "cheese wedge", and have a PCB with decoding & buffering circuitry, and the headers for - depending on loading factors - up to 4 of this kind of module.

The outcome? A 16MB RAM-disc for the Beeb, possibly with battery-backup, if this is possible.

Can I hear somebody say "super-fast HDD replacement"?

--Martin

[ElEctric_EyE]

mdpenny wrote:

...Can I hear somebody say "super-fast HDD replacement"?

--Martin

Don't forget about SSD(Solid State Drives)... Although I don't see any with an IDE I/F, there are some with USB I/F. Maybe they could be coax'ed into working for a 65xxx system?

[mdpenny]

It was just the image that came to mind; I might yet do _something_ along these lines as a (first) electronics project - I'll let the forum know if I get anywhere with the idea.

--Martin

[GARTHWILSON]

Quote:

The outcome? A 16MB RAM-disc for the Beeb, possibly with battery-backup, if this is possible.

Can I hear somebody say "super-fast HDD replacement"?

My HP-71 hand-held computer has a FAT-less file chain in RAM, but you don't have to load files into "main RAM" to run them or do random access on data or whatever. So in that way it's way better than a RAM disc. You can have hundreds of files in the file chain(s), and executables run right there in place, wherever they are. What's more amazing in this basically bug-free design, although it makes for a lot of overhead, is that a program in one file can instruct the OS to resize or delete a file that comes before it, meaning that everything after it gets scooted up or down in memory, changing the addresses, and yet it adjusts it all in the software buffers so that pending return-from-subroutines or subprograms, etc, still return to the right places, regardless of how many you have open at once. This might be possible when we get our 65Org32 going, but probably not with a 6502.

If you just want a solid-state hard-disc equivalent though, a serial flash IC would be far more compact and economical, and not require the battery backing. It just won't be random-access, and it won't be as fast. My SRAM module is particularly for where you want lots of 5V fast true SRAM with no wait states or memory-management complexities.

Edit, over four years later, related but not closely enough for me to make a separate post on this topic here: The poor reliability of SSDs is discussed in another topic, starting with this post.

[GARTHWILSON]

I just ordered some wire-wrap sockets, so now I can provide those as well as soldertail. I'll post a photo of one after they arrive.

I measured the bare-board and connector measured capacitance at viewtopic.php?p=19507#p19507 .