65VM02
- BigDumbDinosaur
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Re: 65VM02
GaBuZoMeu wrote:
But I'm thinking all the talk so far didn't consider true (aggressiv or hostile) multitasking - only cooperative one.
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98% ACK. I just wouldn't say your opinion is curmudgeonly. To me your words sounds "experience battered".
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Please don't misunderstand my words as offending - your work so far and your goal (as far as I understand it) is great - no doubt. And it is already an interesting contribution to the 6502 world. So don't hesitate - go on! 
x86? We ain't got no x86. We don't NEED no stinking x86!
- GARTHWILSON
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Re: 65VM02
BigDumbDinosaur wrote:
GaBuZoMeu wrote:
But I'm thinking all the talk so far didn't consider true (aggressiv or hostile) multitasking - only cooperative one.
Granted, that does not automatically make cooperative multitasking suitable for all multitasking needs; but it does take care of situations where for example a loop is entered whose exit conditions will not be met in a reasonable amount of time.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Re: 65VM02
The Macintosh had cooperative multitasking, and wasn't especially crashy.
- BigDumbDinosaur
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Re: 65VM02
BigEd wrote:
The Macintosh had cooperative multitasking, and wasn't especially crashy.
GARTHWILSON wrote:
The way I envision a cooperative system taking care of this problem is that the cyclic executive loop sets a timer every time it calls a task. As long as the task takes only a reasonable amount of time before giving control back, all is well. Control is never seized, and the task only gives back control when it's at a good pausing point. But if the task goes south, the timer times out and generates an interrupt, and its ISR records that fact and gives control back to the loop.
x86? We ain't got no x86. We don't NEED no stinking x86!
Re: 65VM02
Perfect is the enemy of good.
You can have a fun and useful system without MMU and with cooperative multitasking, especially if you're the only person using it. If a task misbehaves, just hit the reset button and fix it. Let's not discourage people who actually take the effort in creating something.
You can have a fun and useful system without MMU and with cooperative multitasking, especially if you're the only person using it. If a task misbehaves, just hit the reset button and fix it. Let's not discourage people who actually take the effort in creating something.
Re: 65VM02
> Let's not discourage people who actually take the effort in creating something.
Quite so.
Quite so.
- GARTHWILSON
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Re: 65VM02
BigDumbDinosaur wrote:
GARTHWILSON wrote:
The way I envision a cooperative system taking care of this problem is that the cyclic executive loop sets a timer every time it calls a task. As long as the task takes only a reasonable amount of time before giving control back, all is well. Control is never seized, and the task only gives back control when it's at a good pausing point. But if the task goes south, the timer times out and generates an interrupt, and its ISR records that fact and gives control back to the loop.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
- barrym95838
- Posts: 2056
- Joined: 30 Jun 2013
- Location: Sacramento, CA, USA
Re: 65VM02
I like the idea of a cooperative "scheduler" and a preemptive "executioner". I am reminded of the "watchdog" interrupt facility in some small systems.
Mike B.
Mike B.
Re: 65VM02
Arlet wrote:
Perfect is the enemy of good.
Arlet wrote:
You can have a fun and useful system without MMU and with cooperative multitasking, especially if you're the only person using it. If a task misbehaves, just hit the reset button and fix it. Let's not discourage people who actually take the effort in creating something.
If (due to my limited Forth knowledge) I understand Hugh's idea correctly he figured out a neat way to do a sort of "soft task switching" by selecting a frequently used primitive to check whether time is up and then do a switch with minimum housekeeping efforts. Additionally he assist this switchover by some new instructions, accelerating things even more. This looks to me as a very nifty variant of a switchover and perhaps a really new one as well!
BTW: thinking about a bulletproof multitasking does not mean cooperative MT is useless - cooperative MT could be used within a task as well - I think this is commonly called multithreading.
barrym95838 wrote:
I like the idea of a cooperative "scheduler" and a preemptive "executioner". I am reminded of the "watchdog" interrupt facility in some small systems.
Mike B.
Mike B.
Re: 65VM02
I'm a fan of true multi-tasking. Kernels with true multi-tasking don't need to be large and complex. There are several multi-tasking software kernels that are only a few kb in size. I wonder how efficient a co-operative multi-tasker is. With all the checking for task switches seems like it would be less efficient than pre-emptive.
MMU's can vary from really simple to very complex. Simply switching memory banks by holding a bank number in a register can go a long ways towards providing protection of one task from another. Using a typical 512k ram could provide enough memory for 16, 32kb tasks.
MMU's can vary from really simple to very complex. Simply switching memory banks by holding a bank number in a register can go a long ways towards providing protection of one task from another. Using a typical 512k ram could provide enough memory for 16, 32kb tasks.
Re: 65VM02
Rob Finch wrote:
I'm a fan of true multi-tasking. Kernels with true multi-tasking don't need to be large and complex. There are several multi-tasking software kernels that are only a few kb in size. I wonder how efficient a co-operative multi-tasker is. With all the checking for task switches seems like it would be less efficient than pre-emptive.
MMU's can vary from really simple to very complex. Simply switching memory banks by holding a bank number in a register can go a long ways towards providing protection of one task from another. Using a typical 512k ram could provide enough memory for 16, 32kb tasks.
MMU's can vary from really simple to very complex. Simply switching memory banks by holding a bank number in a register can go a long ways towards providing protection of one task from another. Using a typical 512k ram could provide enough memory for 16, 32kb tasks.
(OT: Things are going to become really weird when there is more than one CPU running simultaneously...
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Hugh Aguilar
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Re: 65VM02
BigDumbDinosaur wrote:
Hugh Aguilar wrote:
I wish I had thought of the 65VM02 in the early 1980s, but I was still in high-school at that time. The 65VM02 would have allowed computers such as the Commodore-64 to support a multi-tasking OS. How cool would that have been?
CP/M and MS-DOS would not have become popular --- who would want to use MS-DOS and its TSRs
when a real multi-tasking OS was available on the C64? --- the world would have been a better place!
Anyone who is familiar with the hardware of systems capable of preemptive multitasking knows that the MPU is only part of the equation. What makes preemptive multitasking of the sort implemented with UNIX practical is hardware support for memory protection and different modes of operation. In modern systems, the MPU handles that ("rings of privilege," page tables, etc.). Back in the late 1970s and early 1980s, most systems had dedicated management hardware to enforce memory protection and the trapping of privileged instructions when executing in user mode. A few multitasking machines, most notably the Commodore Amiga, had no dedicated memory management hardware and relied upon careful operating system design to protect the kernel and critical system areas from the effects of dubious programming. However, the Amiga was a one-user system, unlike its contemporaries that ran UNIX, which were designed from scratch to support multiple users running multiple tasks. The Amiga kernel's only real threat was the user and if s/he were dumb enough to run a program that overwrote the kernel, stack, or other system area and crashed the machine (which people did do on occasion), oh well!
BigDumbDinosaur wrote:
I'm not certain what your ultimate goal is with your 65VM02 design, but my curmudgeonly opinion is you will find that an intense focus on the microprocessor without considering how the rest of the targeted system will fit together is not going to produce a satisfactory result. A computer is much more than just an MPU. What about I/O? Oftentimes, the interfacing of I/O hardware to the system is much more complicated than interfacing the microprocessor. Although the 65xx peripheral devices may suffice in a uni-tasking environment, they will probably be inadequate in a multitasking situation, especially the 65C51 UART, which is a very "labor-intensive" device from the perspective of the microprocessor.
The 65VM02 is designed for hard real-time micro-controllers. It supports a multi-tasking OS though, which is for tasks that don't have to be done on a strict schedule (soft real-time).
BigDumbDinosaur wrote:
Also, the focus on Forth will likely narrow the attraction of your design to where it may not be of interest to those who would want to run an operating environment of which Forth would not be a part. The hardware design should not favor one operating environment over another, and should be sufficiently generalized to allow any kind of operating environment to be run, including one with a real-time kernel.
There are processors, such as the MiniForth/RACE that I worked on previously, that were specifically designed to support Forth. The 65VM02 isn't one of them. There should be no difficulty in writing a C, Pascal, or whatever compiler for the 65VM02 --- the code quality should be comparable to Forth in regard to size and speed.
The 65VM02 supports byte-code with these instructions:
Code: Select all
JVM page jump through the pointer located at (page*$100+A)
OPA load A with (IP) in the alternate-bank, then increment IP
EXIP exchange IP with YA
The 65VM02 supports local variables with these instructions:
Code: Select all
LLY load Y with the offset to the bottom value of the return-stack from the page boundary
AAS add A to S
BigDumbDinosaur wrote:
In following your topic, I'm getting the feeling you haven't fully defined what it is the 65VM02 is supposed to do that the 65C02 and 65C816 can't do. Am I misunderstanding?
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Hugh Aguilar
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Re: 65VM02
GaBuZoMeu wrote:
Arlet wrote:
Perfect is the enemy of good.
Arlet wrote:
You can have a fun and useful system without MMU and with cooperative multitasking, especially if you're the only person using it. If a task misbehaves, just hit the reset button and fix it. Let's not discourage people who actually take the effort in creating something.
If (due to my limited Forth knowledge) I understand Hugh's idea correctly he figured out a neat way to do a sort of "soft task switching" by selecting a frequently used primitive to check whether time is up and then do a switch with minimum housekeeping efforts. Additionally he assist this switchover by some new instructions, accelerating things even more. This looks to me as a very nifty variant of a switchover and perhaps a really new one as well!
Previously I had expected to have a T-flag that gets set by the heartbeat timer (either the ISR does this, or it is done by hardware). At NEXT for every primitive (not any particular frequently used primitive), the T-flag is tested and if set a task-switch is done.
I got rid of all that though.
There were problems with that design. Specifically, that accessing some shared resource could only be done inside of a single primitive, which necessarily implied that the code was written in assembly-language. What I have now is the EXA instruction that allows a task to obtain a semaphore. This means that accessing some shared resource can be done in Forth code (or C code or whatever language is being used) --- it doesn't have to be done inside of a single primitive --- the whole point of the 65VM02 is to support high-level languages, so I don't want to force people to use assembly-language for common programming tasks.
I think my design is way beyond the 65c02. I have support for byte-code VM execution which makes a high-level language realistic, I have support for local variables, I have support for semaphores, and I have support for a RAM-disk outside of the 64KB main-bank. The 65c02 lacked support for all of this --- that is why it became obsolete --- it was a very minor upgrade to the 6502; it just wasn't moving forward into the future.
The 65c816 is a much bigger processor than the 65VM02, with 16-bit registers. It doesn't support byte-code VM execution though, so high-level language compilers will typically generate machine-code which is typically quite bloaty. The 65c816 also only has the NMI and IRQ interrupts, the same as the 65c02, so it is pretty weak compared to the 65VM02 that has NMI IRQ MIRQ0 MIRQ1 MIRQ2 MIRQ3 interrupts --- the 65VM02 also allows NMI and IRQ interrupts to interrupt MIRQ ISRs, although the MIRQ interrupts can't interrupt each other's ISRs, so I have a distinction between high-priority and low-priority interrupts.
In the 65VM02 I have the D register that indicates where the direct-page and return-stack are. The D register is always even, so the direct-page will be on an even page and the return-stack will be on the next higher page. By changing D the entire context of a task can be swapped out with that of another task (most tasks use only the direct-page and return-stack for all of their data). This makes for very fast task-switches. The tasks communicate with each other using shared data-structures in the heap (there is 56KB of RAM available in the main-bank, so the heap is pretty big).
The 65VM02 is still an 8-bit processor with 8-bit registers. It is not an upgrade to 16-bit registers like the 65c816. It seems like upgrading from 8-bit to 16-bit registers is obvious. I am dubious that this is a good idea though. To me, the hallmark of the 65c02 was the A X Y and S registers, all 8-bit, and that is what I still have in the 65VM02 (with the addition of the D register that is also 8-bit). This is a small processor! I do have the IP register that is 16-bit, but this is provided to support byte-code VM execution, which is only necessary for high-level languages support.
Having a very few 8-bit registers allows the 65VM02 to have very fast interrupt response time (the IP registers doesn't have to be saved and restored if the ISRs are written in assembly-language, which is the typical case). All in all, I think the 65VM02 is a better design than the MSP430 or STM8 --- those are primarily what it would compete against.
Re: 65VM02
GaBuZoMeu wrote:
Perfect could as well be a driving force to let good advance to better 
- barrym95838
- Posts: 2056
- Joined: 30 Jun 2013
- Location: Sacramento, CA, USA
Re: 65VM02
Arlet wrote:
GaBuZoMeu wrote:
Perfect could as well be a driving force to let good advance to better 
Mike B.