When is a Latch not a Latch? (Capturing the '816 Bank Addr)

[Dr Jefyll]

In this thread I'll share some thoughts on various ways to capture a 65816's Bank Address bits (A23 - A16). The conventional solution -- a 74xx373 (or '573) octal transparent latch -- is certainly workable. However, minor (or not-so-minor) variations will sometimes be a better fit for prevailing priorities and circumstances.

conventional latch.png (3.76 KiB) Viewed 7124 times

I'll begin with a minor variation. The diagram above shows the area of interest in a hypothetical '816 system. But if your plans don't include 16 MB of memory then you can save some PCB real estate by capturing only as many bank bits as you need. Three, two or perhaps even as few as one 1-bit latches (such as 74LVC1G373) may suffice for the job. And, as the photo below shows, the 1G devices are real space savers, even when a breakout board is used. (I talk about the "1G" series of tiny, 6-pin SMD devices here.)

counter 'latch'.png (2.66 KiB) Viewed 7124 times

Shown above is another alternative to a '373/'573. Although the '190, '192, '193 etc aren't usually described as 4-bit latches they nevertheless can function as such (just tie the count and reset inputs to their inactive states).

One potential advantage is the slightly smaller package (16-pin, as opposed to 20 for a '373). Also notable is the polarity of the control input. Unlike a '373 or '1G373, the counter doesn't require an inverted version of PHI2. Sometimes that detail will hardly matter. But in other cases an inverter may not be available, or its prop delay may be deemed objectionable.

Speaking of the polarity of the control input, a '157 or '257 4-bit mux can also serve as a 4-bit latch, and you can have whichever polarity you prefer! As shown below, one set of inputs accepts new data and the other set recirculates what already appears on the chip's own outputs. I'm intrigued by this idea, and feel sure it is viable. However, I don't know how it could be guaranteed to be reliable, given the limited detail in published specs. The necessary info simply isn't included.

157-257 'latch'.png (6.71 KiB) Viewed 6487 times

Using FET Switches and Tristate Buffers as Latches

The scheme shown below bears consideration by anyone intent on running the '816 as fast as it can possibly run!

tristate 'latch'.png (2.49 KiB) Viewed 7124 times

Whereas a conventional latch causes the Bank Address to be delayed according to the latch's propagation delay, the FET switch incurs only a tiny (usually sub-ns ) RC delay based on the ON Resistance of the FET and the capacitance of the load. Getting the Bank Address out sooner means the attached devices (eg: decoders and memory) can respond sooner, which may allow you to boost the clock rate. (Or instead you may wish to spend the extra timing margin by switching to slower, cheaper RAM's.)

As noted, the Bank bits miraculously travel through the FET switch with near-zero delay. We could wish the switch's OE input also acted instantly; but this isn't the case -- it is subject to conventional prop delays. However, this shouldn't be seen as a point against the FET approach. You'll be obliged to account for some sort of enable delay no matter what kind of latch you use. The "win" with the FET switch is getting the Bank Address out sooner.

As drawn, the circuit relies on the capacitance of the attached devices to maintain the Bank Address bits during the clock-high period -- presumably just a fraction of a microsecond. But if clock stopping is a requirement then you can consider attaching a 74ACT1071 or other bus-hold device to indefinitely maintain the bits. Here's a datasheet for the '1071, a 10-bit device. Its cousin the '1073 is 16-bit. (Be aware that, by design, these devices drive the bus weakly. They're not appropriate when significant DC loading is present.)

74act1071 10-bit bus-hold.pdf

(483.31 KiB) Downloaded 275 times

And here's a datasheet for one octal FET bus switch product. Other offerings include 74cb3t3245 and 74cbtlv3245, to name just a couple.

74cbt3245c.pdf

(893.93 KiB) Downloaded 261 times

Changing topic slightly, the bus-capacitance scheme will also work if the FET switch is replaced with an ordinary tri-state buffer (eg: 74xx244). Obviously the benefit of near-zero delay is lost, but the idea could be handy in an emergency. Maybe it's the weekend and you wanna quickly hack something together using only the stuff you already have on hand...

The point mentioned earlier about control signal polarity bears further discussion, but I won't go into detail in this post. Instead I'll simply point out that there may be drawbacks when an inverted clock signal ( /PHI2 ) is required.

-- Jeff

[Chromatix]

And not forgetting that you might want to insert a gate to incorporate the RDY signal into the multiplexing equation; that's likely to invert the polarity of the clock for you. You'll probably also have to insert an inverter in the RDY signal path, but you should have more setup time for that.

[BillO]

I think there is a way to rig this so there is effectively zero propagation delay due to the inverter. Run the oscillator directly to the latch, and run the system clock through the inverter. This way only the latch PD matters. If fast logic is used, like ACT, that PD will be reduced to less than 12ns (6ns typical).

[Dr Jefyll]

Bill, I like your suggestion for effectively zero propagation delay on the clock signal sent to the latch enable. In effect the circuit "predicts" what the clock is about to do. But, as you note, there'll still be the Propagation Delay of the bank bits themselves as they enter and pass through the latch.

Not every '816 application demands utmost speed. But when maximum speed is the goal, I'd be looking to eliminate or sidestep the latch delay.

Unlike the clock, the bank bits can't be predicted -- when a cycle begins they are unknown. And, until they're known, memory can't properly begin to respond. So, in effect, the 5 or 10 ns of latch delay makes memory 5 or 10 ns slower.

Because of the potential to reduce the delay down to just a fraction of a ns my own approach to overclocking an '816 would be as described in the final section of my post above, Using FET Switches and Tristate Buffers as Latches.

-- Jeff

[Dr Jefyll]

in another thread, kernelthread wrote:

The FET switch idea looks interesting. Do you reckon you could combine it with a 74ACT573 to get effectively a <1ns propagation transparent latch? When PHI2=0, the FET switch is on and the 573 has LE=1, OE=1, so the latches are transparent but the outputs are disabled and don't contend with the FET switch. When PHI2=1 the FET switch is off and the 573 has LE=0, OE=0 so it maintains the state previously passed through by the FET switch.

Yup, that sounds like it would work... one of several ways the idea could work, really.

The critical time is at the beginning of the cycle when PHI2 has just fallen. That's when we want the FET switch to very rapidly conduct the newly arriving bank bits from the '816 bus to the system address bus (which drives the RAM, ROM, address decoder and so forth). That's the goal for the PHI2-low period. (And, to be clear, the enable signal sent to the FET switch would need to be advanced by a few ns, much as Bill suggests above. The enable input isn't sub-nanosecond. But -- crucially -- the data path is.)

During the PHI2-high period, we want the system bus to retain the bank bits that've been established. And there are several ways to accomplish that.

I think it'd be kinda cool to simply do nothing... and let bus capacitance passively hold the value! But that solution isn't appropriate in all circumstances. If necessary we could add some circuitry that actively maintains the bank bits that've been established. Your '573 suggestion is an example of this. Other active solutions exist, as noted in the lead post.

-- Jeff

[BigDumbDinosaur]

And there is this variation on the “classic” latch circuit:

I haven’t analyzed it for timing. Also, it doesn’t illustrate what is controlling RDY, which, of course, will add its own timing factors to the mix.

[Dr Jefyll]

I haven't closely analyzed the timing either, but in general terms the goal of this scheme is clear.

And it's even more clear after the thing is redrawn with an emphasis on left-to-right signal flow. I've highlighted two particular signals in color.

Apparently the purpose of the inverters is to introduce some propagation delay comparable to that of the 'AC02. As a result, a rising edge on the 573's LE input will occur at virtually the same instant as a falling edge on the CPU's Phi2 input.

There'll be a brief delay before the CPU responds (by outputting the new cycle's Bank Address), and simultaneously there'll be a brief delay before the '573 responds (by allowing the new Bank Address to be accepted, replacing the one that preceded it).

As shown below, the same sort of strategy can be applied when the '573 is upgraded to a FET Bus Switch. The latter has near-zero propagation delay for the address bits flowing through it, but its /OE control input is still subject to typical, Earthly propagation delays.

-- Jeff

[kernelthread]

The propagation delay from the control input on the FET switches (enable time or disable time) is listed as 4-5 ns. That doesn't seem a big deal to me since it will take the 816 longer than that to produce the bank address (12ns I seem to remember). Provided the FET switch is enabled before the 816 outputs the bank bits they should propagate through the switch very quickly so no overall system delay will result.
A possible issue is what happens at the rising clock edge. The FET switch will be disabled but will take up to 5ns to turn off. If the 816 data bus lines change during that time the 'latched' bank bits could be incorrect.

[BigDumbDinosaur]

kernelthread wrote:

A possible issue is what happens at the rising clock edge. The FET switch will be disabled but will take up to 5ns to turn off. If the 816 data bus lines change during that time the 'latched' bank bits could be incorrect.

Unfortunately, the 65C816’s data sheet is not very helpful in that regard. The controlling timing parameter, which I refer to as the “bus turnaround time,” seems to be missing from the timing chart. I did measure that parameter in POC V1.2 with the logic analyzer, but that was one specific case. Hard to generalize from that.

Above is a capture with POC V1.2 running on 5 volts at 12.5 MHz—the capture is during a data fetch bus cycle. The cycle length is 80ns and the logic analyzer’s resolution is set to 2ns. The apparent bus turnaround time is 8ns.

[Alnitak]

Dr Jefyll wrote:

Apparently the purpose of the inverters is to introduce some propagation delay comparable to that of the 'AC02. As a result, a rising edge on the 573's LE input will occur at virtually the same instant as a falling edge on the CPU's Phi2 input.

After poring through many threads on cycle timings and clock stretching while mulling a potential '02 design, I had been wondering why no-one seemed to be generating the '816 bank address latching signal from a merely delayed PHI2 signal instead of waiting for a rising edge of PHI1. With TBAS at a maximum of 33ns (and I gather more commonly in the region of 12ns on current fab chips) this seemed like a more obvious way of getting the full address as quickly as possible in overclocked systems.

Ray

[Dr Jefyll]

I'm not sure I understand your remarks, Ray. You say no-one seems to generating the '816 bank address latching signal from a merely delayed PHI2 signal, but a delayed PHI2 signal *is* what's used in the diagram I posted. The delay of the 'AC02 is admittedly very short, of course. Can you be more specific, please, about how long a delay you're proposing? I'm afraid don't find your meaning clear.

And you mentioned PHI1, but that's a signal associated with 6502/65C02. An '816 system has no PHI1, just PHI2 and usually also an inverted version of PHI2. (Are you referring to the latter as PHI1?)

-- Jeff

[Alnitak]

Dr Jefyll wrote:

I'm not sure I understand your remarks, Ray. You say no-one seems to generating the '816 bank address latching signal from a merely delayed PHI2 signal, but a delayed PHI2 signal *is* what's used in the diagram I posted. The delay of the 'AC02 is admittedly very short, of course. Can you be more specific, please, about how long a delay you're proposing? I'm afraid don't find your meaning clear.

And you mentioned PHI1, but that's a signal associated with 6502/65C02. An '816 system has no PHI1, just PHI2 and usually also an inverted version of PHI2. (Are you referring to the latter as PHI1?)

-- Jeff

I meant no one seemed to be doing it, except you!

It was slightly edifying to see that I wasn't being completely dumb. And yes, I did mean an inverted PHI2 when I said PHI1.

Ray