[WORKING] Simple 6502 SBC from scratch (Deck65)

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and3rson
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Re: Attempting to build a simple 6502 SBC from scratch

Post by and3rson »

Garth - those "tips of the day" are awesome, thanks for sharing! I've learned a lot of cool tricks there.

Meanwhile, while I'm waiting for my 65C02 to arrive, I've been trying to implement a hexadecimal 7-segment decoder to visualize what's going on at the data bus. Initially I wanted to use GAL20V8. Here's what I came up with:

Code: Select all

GAL20V8
Hex-7Seg

CLK A   B   C   D   A1  B1  C1  D1  NC  NC  GND
/OE NC  Q   a   b   c   d   e   f   g   NC  VCC

a = A*/B*/C + /A*B*D + A*/D + /A*C + B*C + /B*/D
b = /A*/C*/D + /A*C*D + A*/C*D + /B*/C + /B*/D
c = /A*/C + /A*D + /C*D + /A*B + A*/B
d = /A*/B*/D + /B*C*D + B*/C*D + B*C*/D + A*/C
e = /B*/D + C*/D + A*C + A*B
f = /A*B*/C + /C*/D + B*/D + A*/B + A*C
g = /A*B*/C + /B*C + C*/D + A*/B + A*D

DESCRIPTION
Hexadecimal decoder for 7-segment displays
This worked, but I wanted two digits! Unfortunately, I could not use CLK in my GAL20V8 to drive two displays at once since the maximum number of terms in OR is 8, and I'd need to duplicate each of them based on the value of Q register (low = low nibble / right digit, high = high nibble / left digit)
So I decided to try and 1) implement driver with good old 7400 ICs in emulator (because why not?) and 2) try to multiplex lower and higher nibble of 8-bit input to each of the two displays.

I ended up with a huge matrix of AND & OR gates (I heard you guys like *big* schematics!) and simulated it in Digital (https://github.com/hneemann/Digital).

Initially I had 35 terms total, but there were some duplicates, so the final count of AND gates went down to 28:

Code: Select all

>>> terms = re.findall('([A-D*/]+)', s)
['A*/B*/C', '/A*B*D', 'A*/D', '/A*C', 'B*C', '/B*/D', '/A*/C*/D', '/A*C*D', 'A*/C*D', '/B*/C', '/B*/D', '/A*/C', '/A*D', '/C*D', '/A*B', 'A*/B', '/A*/B*/D', '/B*C*D', 'B*/C*D', 'B*C*/D', 'A*/C', '/B*/D', 'C*/D', 'A*C', 'A*B', '/A*B*/C', '/C*/D', 'B*/D', 'A*/B', 'A*C', '/A*B*/C', '/B*C', 'C*/D', 'A*/B', 'A*D']
>>> len(terms)
35
>>> len(set(terms))
28
>>> set(terms)
{'/A*B*D', '/C*D', 'A*/B', '/B*C', '/A*C', 'B*C*/D', 'A*/D', 'A*B', 'A*/C', 'A*D', 'A*/B*/C', '/A*/C', '/B*/D', 'A*C', '/B*/C', 'A*/C*D', '/A*B*/C', '/A*C*D', 'B*C', '/B*C*D', '/A*/C*/D', '/A*D', '/C*/D', 'B*/D', '/A*B', 'C*/D', '/A*/B*/D', 'B*/C*D'}
I then arranged them all in a net of ANDs & ORs:
sevenseg_decoder_bw.png
This seems to work on paper, but I was wondering if I missed anything here. Any tips are appreciated!

Digital circuit:
sevenseg_decoder.zip
(3.79 KiB) Downloaded 77 times
Animated simulation (GIF, click to play):
anim.gif
Last edited by and3rson on Sun Feb 26, 2023 5:52 pm, edited 1 time in total.
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD
barnacle
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Re: Attempting to build a simple 6502 SBC from scratch

Post by barnacle »

Well I was just gobsmacked to see that binary to 7-segment TTL decoders just don't appear to be a thing anymore. Even the bay only shows one 74LS46 and that's in Greece.

Another way of doing it involves a big pile of diodes and something like a pair of LS238 positive going inverters: one line goes high for any binary input; use that into a matrix of diodes to light the required segments (assuming common cathode LEDs - for common anode use the LS138 instead). Or a single LS154 might present a physically smaller option but I don't know of a positive output version. Don't forget a current limiting resistor for each segment!

Neil
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and3rson
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Re: Attempting to build a simple 6502 SBC from scratch

Post by and3rson »

barnacle wrote:
Well I was just gobsmacked to see that binary to 7-segment TTL decoders just don't appear to be a thing anymore. Even the bay only shows one 74LS46 and that's in Greece.

Another way of doing it involves a big pile of diodes and something like a pair of LS238 positive going inverters: one line goes high for any binary input; use that into a matrix of diodes to light the required segments (assuming common cathode LEDs - for common anode use the LS138 instead). Or a single LS154 might present a physically smaller option but I don't know of a positive output version. Don't forget a current limiting resistor for each segment!

Neil
The problem with 74xx is that there are BCD decoders, but no hexadecimal ones. I only found some custom FPGA-based decoders for hex. I wonder if I'm missing something.
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD
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Michael
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Re: Attempting to build a simple 6502 SBC from scratch

Post by Michael »

Do you do anything with microcontrollers, Andrew?
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Michael
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Re: Attempting to build a simple 6502 SBC from scratch

Post by Michael »

and3rson wrote:
The problem with 74xx is that there are BCD decoders, but no hexadecimal ones. I only found some custom FPGA-based decoders for hex. I wonder if I'm missing something.
Are MC14495's still around?
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and3rson
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Re: Attempting to build a simple 6502 SBC from scratch

Post by and3rson »

Michael wrote:
Do you do anything with microcontrollers, Andrew?
Yeah - nice solution! Using PIC would be the easiest way, I think. I still wanted to give a try to 7400-only solution (it also helped me better understand how GALs work), but it really feels like an overkill. I'll probably stick to a single SoC for all 6 digits (4 addr & 2 data).

EDIT: Yes, I found out about MC14495 earlier, but sadly, it seems to be discontinued...
EDIT 2: Seems like ALL common hex decoders are gone now, but BCDs are still around: https://en.m.wikipedia.org/wiki/Seven-s ... ecoder_ICs
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD
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Michael
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Re: Attempting to build a simple 6502 SBC from scratch

Post by Michael »

I thought about doin' something like that, too...
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and3rson
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Re: Attempting to build a simple 6502 SBC from scratch

Post by and3rson »

Michael wrote:
I thought about doin' something like that, too...
That's cool! I've been thinking of taking some cheap attiny with many legs to drive 4 7-seg displays. Attiny88 would work - it has 24 GPIO pins: 16 bits for input (4 nibbles), 6 bits for output (4 displays in parallel) and 2 bits for selecting 1 of 4 displays. To sync with Ф2, attiny88-au can be used - it has 4 more pins. Also, dot can be used to indicate when R/W line is low. However, I'm afraid that attiny's 16 MHz clock might be too slow for this... Feels like all roads lead to FPGA.
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD
plasmo
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Re: Attempting to build a simple 6502 SBC from scratch

Post by plasmo »

CPLD is easier, you don’t need to deal with voltage translation of FPGA.
Bill
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and3rson
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Re: Attempting to build a simple 6502 SBC from scratch

Post by and3rson »

plasmo wrote:
CPLD is easier, you don’t need to deal with voltage translation of FPGA.
Bill
Thanks for the suggestion, I'm new to PLDs, will try it out!

BTW - seems like my addressing glue logic can *almost* entirely fit into a single GAL16V8 (replacing 74xx00 & 74xx138) - that might help save a little bit of PCB space, but I'm not sure if that's worth it. Another perk is that addressing can be reconfigured post-build, allowing for ad-hoc modifications to memory map.
Still, playing with GALs is fun (googling relevant information was even more fun - searching for "gal pins" yielded hilariously irrelevant results).

Code: Select all

GAL16V8
AddrDeco

; For GAL20V8:
; NC   A8   A9   A10  A12  A13  A14  A15  NC   NC   NC   GND
; NC   NC  /RAM /ROM /LCD /VIA /IO2 /IO3 /IO4 /IO5  NC   VCC
NC   A8   A9   A10  A12  A13  A14  A15  NC   GND
NC  /RAM /ROM /LCD /VIA /IO2 /IO3 /IO4 /IO5  VCC

; RAM: First 48k (A15..A14 in 00, 01, 10)
RAM = /A14 + /A15
; ROM: Last 8k (!RAM & A13)
ROM = /RAM * A13
; I/O: $D000-$D5FF (6 x 256-byte segments) - not enough outputs for IO6 & IO7, oh well
LCD = /RAM * /ROM * A12 * /A8 * /A9 * /A10
VIA = /RAM * /ROM * A12 *  A8 * /A9 * /A10
IO2 = /RAM * /ROM * A12 * /A8 *  A9 * /A10
IO3 = /RAM * /ROM * A12 *  A8 *  A9 * /A10
IO4 = /RAM * /ROM * A12 * /A8 * /A9 *  A10
IO5 = /RAM * /ROM * A12 *  A8 * /A9 *  A10

DESCRIPTION
Address Decoder for my 6502 SBC.
EDIT: Seems like Lattice's GALs were discontinued over a decade ago... I'm really "lucky" with my IC choices. Guess I'll try smth like ATF16V8.
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD
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Michael
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Re: Attempting to build a simple 6502 SBC from scratch

Post by Michael »

There are several methods for flexible memory mapping. Here's one of many variations (below) that use 8-bit magnitude comparator chips;

Have fun...
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floobydust
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Re: Attempting to build a simple 6502 SBC from scratch

Post by floobydust »

and3rson wrote:
plasmo wrote:
CPLD is easier, you don’t need to deal with voltage translation of FPGA.
Bill
Thanks for the suggestion, I'm new to PLDs, will try it out!

BTW - seems like my addressing glue logic can *almost* entirely fit into a single GAL16V8 (replacing 74xx00 & 74xx138) - that might help save a little bit of PCB space, but I'm not sure if that's worth it. Another perk is that addressing can be reconfigured post-build, allowing for ad-hoc modifications to memory map.
Still, playing with GALs is fun (googling relevant information was even more fun - searching for "gal pins" yielded hilariously irrelevant results).

Code: Select all

GAL16V8
AddrDeco

; For GAL20V8:
; NC   A8   A9   A10  A12  A13  A14  A15  NC   NC   NC   GND
; NC   NC  /RAM /ROM /LCD /VIA /IO2 /IO3 /IO4 /IO5  NC   VCC
NC   A8   A9   A10  A12  A13  A14  A15  NC   GND
NC  /RAM /ROM /LCD /VIA /IO2 /IO3 /IO4 /IO5  VCC

; RAM: First 48k (A15..A14 in 00, 01, 10)
RAM = /A14 + /A15
; ROM: Last 8k (!RAM & A13)
ROM = /RAM * A13
; I/O: $D000-$D5FF (6 x 256-byte segments) - not enough outputs for IO6 & IO7, oh well
LCD = /RAM * /ROM * A12 * /A8 * /A9 * /A10
VIA = /RAM * /ROM * A12 *  A8 * /A9 * /A10
IO2 = /RAM * /ROM * A12 * /A8 *  A9 * /A10
IO3 = /RAM * /ROM * A12 *  A8 *  A9 * /A10
IO4 = /RAM * /ROM * A12 * /A8 * /A9 *  A10
IO5 = /RAM * /ROM * A12 *  A8 * /A9 *  A10

DESCRIPTION
Address Decoder for my 6502 SBC.
EDIT: Seems like Lattice's GALs were discontinued over a decade ago... I'm really "lucky" with my IC choices. Guess I'll try smth like ATF16V8.
Back in the mid 80's, I settled on a memory map where I used a single page (256 bytes) for an I/O window and could divide it up as 16- I/O selects at 16 bytes wide, or 8- I/O selects at 32-bytes wide. I used 3 74xx logic chips for this: 7400, 7430 and 74138. I did the same in 2013 wqhen I got back into the 65C02 again. I then switched over to a single PLD for all I/O decoding, RAM/ROM selects and clock qualified read and write signals. The 16V8 is a bit light for this, but I would suggest you look at the ATF22V10C. I configure it for 5- I/O selects at 32-bytes wide each, configurable ROM and RAM selects and qualified read and write signals. Here's the base code:

Code: Select all

Name     Glue3 ;
PartNo   01 ;
Date     10/31/2017 ;
Revision 01 ;
Designer KM ;
Company  Analogue Technologies ;
Assembly SBC2 ;
Location  ;
Device   g22v10 ;

/* *************** INPUT PINS *********************/
PIN 1    = CLK                       ; /*                                 */ 
PIN 2    = A15                       ; /*                                 */ 
PIN 3    = A14                       ; /*                                 */ 
PIN 4    = A13                       ; /*                                 */ 
PIN 5    = A12                       ; /*                                 */ 
PIN 6    = A11                       ; /*                                 */ 
PIN 7    = A10                       ; /*                                 */ 
PIN 8    = A9                        ; /*                                 */ 
PIN 9    = A8                        ; /*                                 */ 
PIN 10   = A7                        ; /*                                 */ 
PIN 11   = A6                        ; /*                                 */ 
PIN 13   = A5                        ; /*                                 */ 
PIN 23   = RW                        ; /*                                 */ 

/* *************** OUTPUT PINS *********************/
PIN 14   = !IO1                      ; /*                                 */ 
PIN 15   = !IO2                      ; /*                                 */ 
PIN 16   = !IO3                      ; /*                                 */ 
PIN 17   = !IO4                      ; /*                                 */ 
PIN 18   = !IO5                      ; /*                                 */ 
PIN 19   = !ROM                      ; /*                                 */ 
PIN 20   = !RAM                      ; /*                                 */ 
PIN 21   = !MWR                      ; /*                                 */ 
PIN 22   = !MRD                      ; /*                                 */ 

/** Declarations and Intermediate Variable Definitions  **/
FIELD ADDRESS = [A15..0];

RAM = ADDRESS:['h'0000..DFFF];
IO1 = ADDRESS:['h'FE00..FE1F];
IO2 = ADDRESS:['h'FE20..FE3F];
IO3 = ADDRESS:['h'FE40..FE5F];
IO4 = ADDRESS:['h'FE60..FE7F];
IO5 = ADDRESS:['h'FE80..FE9F];
ROM = ADDRESS:['h'E000..FDFF]
        # ADDRESS:['h'FEA0..FFFF];
/** Logic Equations **/
MWR = (CLK & !RW);
MRD = (CLK & RW);
An extra benefit doing this with the PLD is I only lose the memory addresses that are configured for the 5- I/O selects... the rest of page $FE is still available as ROM. Also, I've still not used all of the available I/O space, but it all depends on what types of hardware devices you're looking to use and what you think your future expansion might include. It's also a benefit to be able to reprogram the PLD and change the mapping. I did that recently when I decided to add more RAM... just swapped to a 128KB SRAM (in place of the 32KB SRAM) and changed the PLD config... 56KB RAM and 8KB ROM (less the I/O selects). Note that the code above is the later code.
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and3rson
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Re: Attempting to build a simple 6502 SBC from scratch (65ad

Post by and3rson »

So I think I screwed up a bit... But I think I've found a way to fix my mistake. :D

No, the board hasn't arrived yet - I've ordered it nearby (I'm lucky to have a PCB printing place within 15-minute drive from my home!) - and it's going to be finished in 1 or 2 days. But I can't change the design since I've already submitted it for printing.

I decided to spend some time reading about HD44780 and suddenly realized two issues:
- HD44780's Enable is active high. I can't believe that flew under my radar!
- HD44780 latches data bus during falling edge of E. This means that I cannot drive E with my '138 since it's not synchronized with Ф2, and data bus will likely be invalid by the time E falls low (due to address change, some time AFTER Ф2 goes low for the next cycle.)

And yes - this was highlighted in "Implementing a Character LCD Module" by Chris Ward. And I read it. And I still missed it. :-|

So my solution is to add Ф2 to the mix as Chris mentions in the article. Luckily, I used 3 our of 4 gates in both of my NANDs, so I can invert output from '138 with one spare gate and NAND it with Ф2 via a second spare gate.
In my PCB, that would mean cutting a trace from '138 to LCD/EN and re-routing it via two NANDs, thus putting those spare gates to good use & syncing LCD/EN.
At this point I realized that I'm still having LCD/EN as active-low. So I'm short on 1 inverter, unfortunately. Guess I'll have to solder it somewhere near the LCD.

Alternatively, I think I could use a single NOR gate as such: LCDEN = NOR(LCD/EN, Ф1) - since Ф1 is just inverted Ф2, and datasheet for WDC's w65c02 mentions that both Ф1 & Ф2 have 22ns delay from Ф0, so they must be in "perfect" sync. Unfortunately, my PCB has no NORs. Oh well, today I learned. :) Still, I think that NOR can be made with 2 diodes, a NAND, and a pull-up: LCDEN = NOT(Ф1 DIODE_OR PULLUP(LCD/EN)). Will this work?

EDIT: Totally forgot to mention my big news - I've got those w65c02s boys (and some axial capacitors for my C64-s) from Mouser today! 5 days from TX to Ukraine via France & Poland - not bad at all!!! This was my second experience with our new international carrier, and man, do they deliver fast! Basically I've ordered the package to be shipped to carrier's warehouse in Poland, and they forwarded it to a post office near my place. The shipping from TX to Poland was free, and from Poland to Ukraine it was ~1.50 USD (shipping small packages from Poland is ridiculously cheap). No tax clearance was required in Poland since it was a transfer.

EDIT 2: I've also received a request from Mouser to fill in some forms related to export of goods from US for my second purchase (VIA + ACIA + misc stuff) which has not yet been shipped. One is EUC Form, the other is Freight Forwarder Certificate. I've filled & returned them to Mouser. Any thoughts on why did they want it all of a sudden would be greatly appreciated. Am I violating anything? I hope I'm not! Because oh boy, with those low shipping costs & fast deliveries I'm going to buy stuff from Mouser every weekend.
Attachments
lcd_fix.png
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD
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Dr Jefyll
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Re: Attempting to build a simple 6502 SBC from scratch (65ad

Post by Dr Jefyll »

Quote:
I've also received a request from Mouser to fill in some forms related to export of goods from US [...] Am I violating anything?
Here in Canada I too was once asked to fill in export forms related to some WDC chips I purchased from Mouser. It struck me as being pretty ridiculous, given that WDC products are not what I'd call sensitive technology... something that would change the balance of military power between nations, for example! :lol:

Anyway, I can't see you getting in any trouble as long as you tell the truth, which is that you're building a hobby project.

-- Jeff
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
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Michael
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Re: Attempting to build a simple 6502 SBC from scratch (65ad

Post by Michael »

Maybe consider an LCD Backpack and drive it using a few pins on the VIA? It might free up some space on your main board. JLCPCB has a once-per-month $8 off promotion for boards designed using their EasyEDA package and I tried it awhile back and got 10 Backpack PCB's for $1, including shipping.
Attachments
LCD Backpack 3-pin.png
LCD Backpack PCB.png
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