6522 VIA Timing

[sburrow]

Hello everyone!

So I've been testing things out on my new board, and my "6522 VIA Expansion" is just not working.

I think the problem might be a timing issue. Attached is what is going on. My CS1 is always high, thus enabled. My CS2B is low for the first half of the cycle (that is the 6502's PHI2-low), thus always enabled, but there is no clock present there. For the second half of the cycle (that is the 6502's PHI2-high), the CS2B is either high (disabled) or low (enabled). During the second half of the cycle, the clock pulses.

I know this is a weird situation.

From my monitor, I am getting floating values from the VIA, all the time. I write to it, I read from it, just floating values, as if nothing is plugged in. It is likewise not responding to anything else. I've put a scope to some of it, everything seems to work as expected EXCEPT for the R/W line. Strangely, when I probe that line while the VIA is plugged in to it, it freaks out and glitches my system, reading high on the probe. But, I probe the R/W line when the VIA is disconnected entirely and it reads as expected. Maybe that's a clue?

The R/W line is unqualified, the /RES line is working fine, etc etc.

Am I missing something? Will the VIA do anything or even care if it is enabled as long as there is no clock pulse?

Any ideas or suggestions?

Thanks!

EDIT:

Two new findings:

1) The signals from the computer definitely work. I was able to use a '373 and '138 with the existing signals to make simple output bits.

2) I used the '138 with 6502-PHI2 and other signals to clean up the enable signal. I finally got a response from the VIA! But it was momentary and reverted to the floating state almost immediately. The enable line isn't exactly perfect either, I still see it enabling the VIA when it shouldn't, but never during a clock pulse.

Any thoughts are appreciated. Thanks!

EDIT2:

I was looking through the W65C22S datasheet, and I found this little phrase:

"RWB must always be preceded by a proper level on CS1, CS2B."

But then I went to the timing diagrams, and I see R/W changing at the same time as CS1 and CS2B. I am very confused about this.

Chad

[BigDumbDinosaur]

sburrow wrote:

So I've been testing things out on my new board, and my "6522 VIA Expansion" is just not working.

A picture is worth a 1000 words. Gotta a schematic?

[sburrow]

Thank you BDD, here is the... *ponders* Wait a minute... *types some code*

AH! Well, I don't know *exactly* what was wrong, but I think it's my darned monitor messing things up! When I just typed some assembly code, whelp, it worked the first time. Got a blinking light from PA0 and everything.

Thanks BDD, you solved my problem by forcing me to look back at what I had, and then make adjustments. You just made my day!

(Still attaching my schematics and updated timing diagram.)

EDIT: Going to show results on my main topic (here viewtopic.php?f=4&t=7407&start=45).

Chad

[BigDumbDinosaur]

Why are you qualifying the VIA’s chip select with Ø2?

[Paganini]

I too am curious about these clock shenanigans. Your prescaler seems to set the VIA up to run twice as fast as the processor, but with a wait state every other cycle. How come?

[sburrow]

Paganini wrote:

I too am curious about these clock shenanigans. Your prescaler seems to set the VIA up to run twice as fast as the processor, but with a wait state every other cycle. How come?

BigDumbDinosaur wrote:

Why are you qualifying the VIA’s chip select with Ø2?

Great questions!

So, my video circuit takes the 6502 offline during PHI2-low. When it comes back on, the address and data buses also come online. I already need to qualify RAM to the second half of PHI2-high to let the address and data buses settle. Same too with the VIA, if I had connected it's PHI2 directly to the 6502's PHI2, it would rise when the addresses and data buses are unstable.

I tested it out and you do not need to connect CS1 to PHI2. It works without that, but I decided it would be more 'safe' because it's being enabled while PHI2-low sometimes due to the video circuit (though no clock exists so nothing happens).

Anyways, the clock rises when the buses and stable, it falls on when PHI2 falls, just as it should when normally working with the 6502.

Does that answer the question?

Chad

[sburrow]

It's been a bit, but I have some updates:

I've been testing the VIA only to write stuff. Apparently that was not good enough, because reading is now an issue. I have LED's connected to PA here. Here is an example:

Code: Select all

LDA #$FF
STA via_da
STA via_pa

Good, all the LED's light up. Super easy. But what if I did:

Code: Select all

LDA via_pa

Oops! The LED's turned off. Why? Well, I don't really know actually. But when I try:

Code: Select all

LDA #$FF
STA via_pa

Um, the lights still are not turning on. I have to start from the very beginning to turn them on again. Thus, DA is getting affected whenever I *read* from PA.

When I'm actually reading what comes from PA, at all, input or output modes, I'm getting either 00 or 55, occasionally something else that looks like trash. I tried connecting PA0 to VCC directly, and it was reading the same thing, no hint of actually seeing what is on PA0.

I know my timing on this thing is weird, I get that. But I find it very strange that reading from PA causes DA to change at all. Could the VIA be resetting or something weird? Any thoughts on what I should start investigating? Anybody else had this type of behavior before?

Thank you everyone.

Chad

EDIT:

I tried a lot of things this morning. But most interesting was when I yanked the /RES line out of the breadboard, and manually brought it low and then high on my own, then left it connected to VCC. And... it's no longer resetting after I read from it! But it is still reading garbage, but what was written is no longer erased. (Funny, after I powered down, then powered back up a few minutes later, the VIA was in exactly the same state as before, just funny how that works.)

I am starting to develop a hypothesis, but it's in the postulate phase right now: Breadboard issues, again... If so, grrrrrrrrrr

[Dr Jefyll]

Chad, re the code you posted, can I assume that via_pa is the VIA's PortA I/O register, and via_da is the VIA's PortA Data Direction register? Just checking.

Also I had an urge to peek at your schematic, but I don't readily find anything I can immediately identify as the latest version. But you say, "my video circuit takes the 6502 offline during PHI2-low." The wording is a tad vague.

In any case, here's your diagram again, and I think you know the VIA needs stable inputs during the interval that's highlighted. *All* the VIA bus control inputs (ie; all the VIA inputs other than the 16 port lines and 4 port handshake lines) need to be stable. In particular I'm wondering about R/W aka RWB.

If you're confident that the logic ought to provide stable inputs, then we need to consider other trouble sources such as power supply noise, or construction errors (who knows, maybe a floating input that somehow got overlooked) -- you get the idea. Good luck!

-- Jeff.

[sburrow]

Dr Jefyll wrote:

Chad, re the code you posted, can I assume that via_pa is the VIA's PortA I/O register, and via_da is the VIA's PortA Data Direction register? Just checking.
Also I had an urge to peek at your schematic, but I don't readily find anything I can immediately identify as the latest version. But you say, "my video circuit takes the 6502 offline during PHI2-low." The wording is a tad vague.
In any case, here's your diagram again, and I think you know the VIA needs stable inputs during the interval that's highlighted. *All* the VIA bus control inputs (ie; all the VIA inputs other than the 16 port lines and 4 port handshake lines) need to be stable. In particular I'm wondering about R/W aka RWB.
If you're confident that the logic ought to provide stable inputs, then we need to consider other trouble sources such as power supply noise, or construction errors (who knows, maybe a floating input that somehow got overlooked) -- you get the idea. Good luck!
-- Jeff.

Thank you Jeff. I have been pondering it all day.

1) Yes, via_pa = via+$01, and via_da = via+$03.
2) Yes, you are right, and I believe I have accounted for the need for stable inputs before the VIA's clock rises.
3) Yes, the R/W line is floating for a bit. I have a pull-up resistor on it, but it isn't needed as per the logic. It is not floating while PHI2 is high, which is when the VIA (in my configuration) will need it.

So, I can half rule out the breadboard as an issue: I just soldered a DIP-40 socket to the board and ran all the bodge wires. It is no longer resetting the VIA when reading. So there's something at least. I can still write to it without issue. Reading gives me the exact same thing: garbage. I installed a SPST switch to be able to manually turn the VIA off whenever I wanted, and I see similar garbage when I try to read while it's disabled. That is telling me that the data bus is floating when the 6502 is trying to read from it, that is the PHI2-falling edge.

Addresses and R/W need to be ready when the VIA's clock rises. I am very sure about that happening, obviously I can write to it. Data needs to be ready when the VIA's clock falls. It seems that VIA-incoming data is fine, but VIA-outgoing data is not. *sigh* Any suggestions are welcome, I'll be pondering on it more.

Thank you Jeff, and thank you all.

Chad

EDIT: I just changed the timing on the CS lines. CS1 (active high) is now active all through PHI2 high and the first half of PHI2 low. Plenty of time for the VIA to output and the 6502 to read. /CS2 (active low) is through address decoding, usual procedure. No changes. Still able to write, not able to read. The R/W line has a pull-up resistor on it, and although it 'floats' at the beginning of PHI2 low, if it were reading, it would stay high anyways. Obviously addresses are solid because I can write. And obviously the 6502 can typically read because it's RAM and ROM work perfectly fine.

Oh, and I tried a second VIA, and it was doing the exact same thing, so it's not the chip's fault.

[sburrow]

Found the problem! Bus contention! Kindof

I put my I/O space on top of where some RAM is normally. When I enable my I/O, the RAM is disabled. So the chip itself is not sending data. BUT the '245 transceiver is!!! Yep. So when I was writing, it was also traveling through the '245 to basically nothing. But when reading, the '245 was trying to send back info on the data bus. Thing is, it was trying to send the result of floating values from the RAM that was turned off. It wasn't floating because the '245 was driving it, just as whatever level it felt was appropriate.

So I switched my VIA's data lines to behind the '245, and it worked the very first time. Boom!

Well, thank you everyone, glad that's over.

Chad

[fachat]

Also, not sure if that is considered.

The VIA wants its address lines stable _before_ phi2 goes high and during phi2 high.
That prevents its direct use in the C64, which shares the bus between VIC-II (phi2 low) and CPU (phi2 high). To make it work reliably, you have to delay the lo/high transition a bit.