Dummy ISR for VIA

[gfoot]

sburrow wrote:

I'm just confused about all of this. Could you explain for a newbie like me? I have heard or-wired and and-gated a lot, not sure what is what honestly.. I use AND gates here because if either signal goes low, the result goes low. I don't understand why OR would be used at all, but then again I'm new at this. I only think in schematics, so perhaps I missed something in digital logic school.

What they're saying is that if the signals were active-high then you would want your gate to output high if either input 1 OR input 2 was high. But they are active low, so AND is what you want here.

In a mathematical sense, AND and OR are duals of each other - they do the same thing in different universes, those being the "positive logic" and "negative logic" universes. If you invert both inputs and the outputs, you turn one into the other! In logic this is called de Morgan equivalence.

Wire-OR refers to the way that if you join two wires together, which are either floating or grounded, then the result is grounded if either of the inputs were grounded - so for devices that with open-collector or open-drain outputs - i.e. the device either connects its output pin to ground or doesn't - you can OR their outputs together by just joining the wires. But you also need a pull-up resistor in case none of the devices is grounding the output, otherwise it just floats.

[Alarm Siren]

sburrow wrote:

I'm just confused about all of this. Could you explain for a newbie like me? I have heard or-wired and and-gated a lot, not sure what is what honestly.. I use AND gates here because if either signal goes low, the result goes low. I don't understand why OR would be used at all, but then again I'm new at this. I only think in schematics, so perhaps I missed something in digital logic school.

...

...

Oh wait, I never went to school for this

Thank you for any clarification.

Chad

I'm sorry that I've caused confusion, its not relevant to your problem, where you have already used the correct gate.
However, I will try to explain what I'm getting at as it might be educational for you.

Instead of thinking of the state of the IRQ signals as "low" or "high", instead replace that with "asserted" or "deasserted", respectively.
Now, when you're combining two IRQ signals you want the output to be asserted when either of its inputs are asserted. Sounds like the function you're implementing is an 'OR' and, at a conceptual level, that's exactly what you're doing when you think about it - you want the processor to interrupt when either VIA 1 or VIA 2 asks for an interrupt.

However, in the actual hardware the asserted state is represented by a low voltage level, so we can't actually use an OR-gate chip here: we'll use an AND-gate chip. The names of the chips, OR/AND/XOR/NAND/whatever, are assuming asserted is represented by a high, but that doesn't mean we have to use them that way. When dealing with active-low signals an OR hardware gate implements the AND function and vice-versa.

If you need to convert between active-high and active-low, you can just stick a NOT on the output. For example, if you had two active-low IRQ signals but your processor needed an active-high INT input, you could use a NAND gate.

[BigDumbDinosaur]

sburrow wrote:

Oh wait, I never went to school for this

Thank you for any clarification.

Chad

Don’t feel badly. I never went to school for this stuff as well. Most of it didn't exist as we know it when I was in school.

[sburrow]

gfoot wrote:

In logic this is called de Morgan equivalence.

Ah yes, de Morgan's Law. We do this in some of our math classes. It applies in other weird places too.

gfoot wrote:

Wire-OR refers to the way that if you join two wires together, which are either floating or grounded,

So that's like an SPI-MISO line right? At least that's what I think of when you talk about it. Everyone is connected to the same line directly.

Alarm Siren wrote:

instead replace that with "asserted" or "deasserted", respectively.

Alarm Siren wrote:

you want the processor to interrupt when either VIA 1 or VIA 2 asks for an interrupt.

That makes sense for sure, thank you for the clarification. I still find it weird terminology, but that is definitely not my strong point anyways. I don't know ANY programming terminology at all, but that doesn't mean I can't code! It is good to know though, thank you. Good explanation.

BigDumbDinosaur wrote:

Don’t feel badly. I never went to school for this stuff as well. Most of it didn't exist as we know it when I was in school.

Me being a math teacher is a blessing because math doesn't change. (Don't listen to folks talk about 'new math'!!!) I feel sorry for my computer science peers who have to keep going to trainings to be able to teach new classes. I remember learning Fortran and COBOL on a mainframe computer my freshman year of college (that is, 2003 btw). Even then that was severely outdated, yet the same teachers who taught me are still teaching today, but other things like Python.

Thank you everyone!

Chad

[GARTHWILSON]

sburrow wrote:

gfoot wrote:

Wire-OR refers to the way that if you join two wires together, which are either floating or grounded,

So that's like an SPI-MISO line right?  At least that's what I think of when you talk about it. Everyone is connected to the same line directly.

No, SPI's lines are all totem-pole, ie, an output can pull up as well as down, and devices' MISO lines are high-impedance (pulling neither up nor down) when they're not selected.  The better comparison would be I²C.  (I²C's passive pull-ups are also why I²C is at such a speed disadvantage compared to SPI.)

sburrow wrote:

(Don't listen to folks talk about 'new math'!!!)

Even in the 1970's, I remember a teacher criticizing 'new math' saying, "They tell you 2+3 equals 3+2, but they never tell you it's 5."  Not many years ago, I was commonly seeing the follies of Common Core.  Wow, that stuff if bad!!

[Paganini]

Hi Chad,

Well, it's Garth's diagram, but since I posted it I will take a stab at clarifying. Sorry if I caused confusion!

Back in ye olden times 65c22 VIAs had an open drain output on IRQ\. They could take the IRQ\ line low if it was high, but they couldn't drive it high if it was low. So, what you did was put a pull-up resistor on the CPU's IRQ\ pin. All the open-drain IC's could then share the same wire to the IRQ\ pin without any additional logic ("wire-or") and any of them could take the IRQ\ line low. The IRQ\ line would *stay low* until the CPU had cleared all of the interrupts from however many devices had gone off at (more or less) the same time. This was easy to implement, but it had a disadvantage: the IRQ\ line was slow to float back up after being cleared, which could lead to some problems, especially at higher clock speeds.

WDC still makes the the 65c22 with open-drain outputs (with the "N" suffix, I think) but the more common "S" suffix chip can both push *and* pull.

I learned all about this last year with Blue April when, not knowing about open-drain outputs, I wire-ored up two "S" suffix WDC65C22 VIAs and then spent a frustrating time trying to figure out why my interrupts suddenly stopped working. It was because they were constantly fighting each other over the wire!

The way to get two (or more) "S" suffix VIAs to work together is to "AND" together their outputs. As long as they are all driving high, the output of the AND gate will be high, which will keep IRQ\high. Any time one of them goes low the output of the AND gate will go low, issuing an interrupt.

If you have to mix & match with open-drain chips, they will all still need their normal pull-up resistor, like usual. You feed their single shared ("wire-ored") line into the AND gate so if any of them take their line low, the AND gate will go low too.

There's another way to do this with a diode that Garth details someplace deep in the primer, but I didn't try that one out last time, so I don't remember exactly how it works.

I think George's point is that if you want to actually *unplug* your VIAs, you will need to add more pull-ups to keep their "AND" gate inputs high while they're gone.

Sorry again for muddying things up!

[Alarm Siren]

sburrow wrote:

That makes sense for sure, thank you for the clarification. I still find it weird terminology, but that is definitely not my strong point anyways. I don't know ANY programming terminology at all, but that doesn't mean I can't code! It is good to know though, thank you. Good explanation.

I'm glad it was helpful, I wasn't sure I'd explained it well enough! Really its just a way of abstracting away the details of the actual hardware implementation and concentrating on the logic you're trying to implement.

In more complex circuits, especially if they switch between active-high and active-low in different parts, it can be a real headache to work out what's going on. If you abstract to Asserted and Deasserted (and thus don't worry about high/low) you can work out the core logic. Once you've done that its easy enough to replace gates as necessary to match with active-high/active-low where each is needed.

You might ask "well why not just have everything be active high, and avoid all this confusion?" In some cases you could do this, but other times there are other considerations that decide one way or the other. For example: in very olden times, pre-CMOS, your typical TTL logic chips could drive low much stronger than they could pull high. Another Example: in an instance where two devices on different voltage levels must communicate it is easier to have the receiver pull-up to their native voltage and then have the driver assert the line by pulling it low - the opposite would require some kind of buffer, which is doable and sometimes preferable, but more expensive.

[GARTHWILSON]

Alarm Siren wrote:

You might ask "well why not just have everything be active high, and avoid all this confusion?" In some cases you could do this, but other times there are other considerations that decide one way or the other. For example: in very olden times, pre-CMOS, your typical TTL logic chips could drive low much stronger than they could pull high.

...and my understanding from decades ago—although I don't get into the wafer-fab physics—was that in bipolar junction transistors, the NPN transistors (as used in TTL) were inherently faster than PNP which would be needed to pull up hard.

[sburrow]

GARTHWILSON wrote:

No, SPI's lines are all totem-pole,

Yet another term! I've heard that before too, now that makes sense.

Paganini wrote:

Back in ye olden times 65c22 VIAs had an open drain output on IRQ\

Paganini wrote:

the more common "S" suffix chip can both push *and* pull.

I do remember this myself. I had an "N" on my first board, and it worked fine. I later tried that "N" in another board and it did not work at all. Probably for this reason. (BTW, are W65C51's more commonly "N"s? I couldn't find an "S" being sold on Mouser.)

Paganini wrote:

you will need to add more pull-ups to keep their "AND" gate inputs high while they're gone.

Definitely!

Alarm Siren wrote:

You might ask "well why not just have everything be active high, and avoid all this confusion?"

GARTHWILSON wrote:

were inherently faster than PNP which would be needed to pull up hard.

There are reasons for all of the chips doing their own thing. I think it's annoying sometimes when I want it a particular way, but that's why we have NOT gates I suppose.

Thank you all very much!

Chad